GB2211000A

GB2211000A - Control circuitry

Info

Publication number: GB2211000A
Application number: GB8823539A
Authority: GB
Inventors: Fred Leverne Lehman; Jr Albert Evariste Barrett
Original assignee: Instron Corp
Current assignee: Instron Corp
Priority date: 1987-10-09
Filing date: 1988-10-06
Publication date: 1989-06-21
Anticipated expiration: 2008-10-06
Also published as: DE3834199A1; GB2211000B; FR2621714A1; JPH01109403A; GB8823539D0

Description

CONTROL CIRCUITRY 2 22U 0 0 The invention relates to circuitry for

providing high speed control of a plurality of control ition transducer, a elements, e.g., an actuator and a posi load transducer, and strain transducers of a material-testing load ft-ame.

one application employing closed loop control is a material-testing load frame, which tests stress-strain characteristics of a sample of a material by subjecting the sample to a force using an actuator and sensing the resulting strain of sample using one or more strain guages. - Depending on the type of test, the sample can be subjected to compression, tension, or alternately to both, employing various waveforms and/or frequencies, as desired. The closed loop control involves adjusting the control signal applied to the actuator in response to an error signal based upon comparison of an expected response signal with a signal or signals from a position transducer, a load transducer and/or one or more strain transducers.

The closed-loop control of load-frames has typically involved analog control circuitry; digital processing has also been used to adjust potentiometers of the analog control circuitry.

we have -discovered that reliable, high-speed, interactive control can be provided for a plurality of control elements (e.g., an actuator and a position transducer, a load transducer, and strain transducers of a material -testing load f rame) by providing a separate, microprocessor-based local control circuit for each control element.

According to a first aspect of the present invention, there is provided circuitry for providing interactive control of a plurality of control elements, comprising: a plurality of control elements having specified functions; a plurality of local control circuits adapted to control respective said control elements; each said local control circuit including a processor adapted for operatively controlling operation of said local control circuit and its respective said control element, a local bus connected to said processor and adapted to provide communication within said local control circuit, a message RAM connected to said local bus, and a control element interface connected between said local bus and said respective control element; a system bus connected to said message RAMs in said local control circuits; and a broadcasting circuit adapted for operatively transmitting messages over said system bus to said message RAMs.

In preferred embodiments broadcasting circuits are located on the local control circuits; the messages are transmitted to predetermined memory locations corresponding to the nature of the message; the local control circuits include means to identify the arrival of messages in selected predetermined memory locations; the means to identify includes an interrupt RAM having addresses corresponding to the predetermined memory locations and means to send an interrupt request to the local processor; there is a system bus arbiter that limits access to the system to one of the broadcast circuits at a time; a broadcast circuit ceases transmission of a message only after receiving an 3 acknowledgement signal from all local control circuits; there is a message RAM arbiter that limits access to the message RAM to either the broadcast circuit or the processor in the local control circuit at one time; the control elements include at least one actuator and at least one transducer; and the transducer senses the response of the actuator to a command signal, the local control circuit for the transducer is programmed to broadcast a message indicating the response via its broadcast circuit, and the processors of the local control circuit for the actuator is programmed to read the message and use it in closed loop control of the actuator.

In a second and alternative aspect, the invention provides control circuitry for a materialtesting load frame, comprising: a plurality of control elements having specified functions, said control elements including an actuator adapted for applying force to a material sample, a load transducer adapted for operatively sensing the load being applied by said actuator, and a strain transducer adapted for operatively sensing strain of said material sample; a plurality of local control circuits adapted for controlling respective said control elements, each said local control circuit including a processor adapted for controlling operation of said local control circuit and its respective said control element, a local bus connected to said processor and adapted to provide communication within said local control circuitt a message RAM connected to said local bus, and said respective control element; a system bus donnected to said message RAms in said local circuits; and a broadcasting circuit adapted for operatively transmitting messages over said system bus to said message RAMs.

4 The invention is hereinafter more particularly described by way of example only with reference to the accompanying drawings, in which:- Fig. 1 is a block diagram of an embodiment of circuitry constructed according to the present invention for controlling control elements of a mater 11al -testing load frame; and Fig. 2 is a block diagram of one of a plurality of local control circuits of the Fig. 1 circuitry.

Referring to Fig. 1, there is shown circuitry 10 for providing closed loop control of a materialtesting load-frame of the generally type disclosed in our British Patent Application 8721862 (Publication No. 2196745). The load frame includes load cell actuator 12 (for applying a force to a material sample under test), load transducer 14 (for sensing the load being applied), position transducer 16 for (sensing the position of the actuator), and strain transducers 18, 20 (for sensing strains at two different locations of the material sample under test), these components being referred to as "control elements" herein. Each control element 12, 14, 16, 18, 20 has an identical, respective local control circuit 22, 24, 26, 28, 30. Each local control circuit includes a microprocessor 32, a local bus 23 (providing local communication between the microprocessor, control element and the rest of the local circuit), a dual-port message RAM 36, and a 5; 1 C broadcast circuit 38. Each dual-port message RAM 36 has one port connected to local bus 34 for reading from and writing to by microprocessor 32.and another port connected to system bus 40 in order to be written to by broadcast circuits 38 of the same or other local control circuits. Local control circuit 22 finctions-both as a master, handling communications with front panel 42 and computer 44, and also as.a.controller for actuator 12. The remaining local control circuits 24, 26, 28, 30 function as conditioners for their respective transducers.

Referring to Fig. 2, local control circuit 22, also referred to as a "core", is shown: the other local control circuits are identical. The core is physically and electrically a template which is placed onto a printed circuit board before any special-purpose circuitry is added for the particular control element or function of the core. Local control circuit 22 has two basic functional parts: diagnostic care 46 and local core 48.

Diagnostic care 46 includes circuitry required to run microprocessor 32 (Motorola 68000,12 MHz) and execute diagnostic self-tests. Diagnostic core 46 includes CPU reset circuit 52, CPU timing and control circuits 54, interrupt control circuit 56 (including an interrupt prioritizer and an interrupt acknowledge generator), core memory 58 (including up to 12.8 K words of program memory that is specific to the operation of the particular local control circuit and up to 64 K Words of high-speed, low-power CMOS RAM for data storage), diagnostic circuits 60, local bus buffers 62 (including high current drivers for post processdr address and control lines, and a transceiver for all data lines to drive and isolate all circuitry outside 6 diagnostic core 46), address decoder 64, and address, control and data lines 66, 68,. 70 of microprocessor 32.

Local core 48 links processor 32 to applications hardware 50 (for interfacing with actuator 12) and to the other local control circuits 24, 26, 28, via system bus 40 (a VME bus). Local core 48 communicates with diagnostic core 4-6 via local bus 34, including address, control. and data lines 72, 74, 76, which are direct, buffered extensions of corresponding lines 66, 68, 70 of microprocessor 32. Lines 72, 74, 76 are connected to broadcast circuit 38, which is in turn connected to system bus 40 via transceivers 78, used to transfer data to and receive data from system bus 40.

VME bus requester/arbiter 80 includes a requester function, which is operational in all local control circuits 22-30, and an arbiter function, which is enabled on only one local control circuit. VME bus requester/arbiter 80 is connected to a system bus request line (used by a local control circuit to request bus mastership in order to broadcast over it) and a grant line (used by the arbiter function to grant a request).

Dual-port message RAM 36 (CMOS static RAMs) has two sets of external address,.data and control line buffers to allow random access from both local bus 34 (both read and write capabilities) and system bus 40 (write capability only). Dual-port RAM arbiter 82 is connected and adapted to prevent simultaneous access to dual-port message RAM 36; the memory ports are normally -disabled and remain so until arbiter 82 grants access. Dual-port RAM bus receivers 84 are connected to transfer data unidirectionally from system bus 40 to dual-port message RAM 36 and to address local interrupt RAM 86. The addresses of RAM 36 are split-up into 256 message r 7 ports represented as individually addressable four-word blocks; each message port is assigned to receive a particular message, and each local control circuit has associated with it a subset of the total number of message ports. RAM 86 is loaded with 4-bit tag words at addresses corresponding to message ports used by local circuit 22: RAM 86 is used with local interrupt input port 88 to indicate that'a-message has just been written into a message port (address) of RAM 36 used for a message that is relevant to the operation of local control circuit 22.

Address decoder 90 decodes addresses on local address lines 72 of local bus 34, and general purpose programmable timers 92 provide timing for local core 48.

Prior to material testing, during initialization, local interrupt RAMs 86 are loaded with tag words at the addresses corresponding to the message ports (addresses for four-word blocks) of dual port RAMs f 36. During testing, actuator 12 applies tension and/or compression to.the sample; load transducer 14 monitors the load actually applied; position transducer 16 monitors the position of actuator 12; and strain transducers 18, 20 monitor the strains at respective locations of the material sample.

In performing these functions,.each control element (i.e., actuator 12, load transducer 14-, position transducer 16, or strain transducer 18 or 20) operates under local control by its respective processor 32 hccording to program instructions in PROM in core memory 58. Control from processor 32 is totally within local circuit 22 and is communicated via local bus 34 nd respective local bus hardware (e.g., analog-to-digital converters) used to interface the digital signals with .4 the control element. Data RAms in core memories 58 are used to store data. e.g., strain information from a strain transducer 18 or 20.

Actuator 12 is operated under closed loop control so as to approach a commanded operation, e.g., a desired waveform synthesized according to its program in its core memory 58. The closed loop control involves comparing an actual response signal based upon the load, position, and/or strains sensed by transducers 14.0 16, 18, 20 with an expected (i.e., commanded) response in order to obtain an error signal used to adjust a control signal to actuator 12.

Every 1 millisecond the load, position (also referred to as stroke), and strains are sampled and broadcast as 4-word messages by respective broadcast circuits 38 to the same addresses (i.e., message ports) in all dual-port RAMs 36. The command signal and error signal, calculated every 1 millisecond and used to adjust the control signal provided to actuator 14 are similarly broadc'ast by broadcast circuit 38 in local control circuit 22 eve.ry 1 millisecond. As illustrated in Fig. 1, the same messages are written to the same locations in all dual-port RAMs 36; only those messages that are relevant to the operation of particular local control circuit 22, 24, 26, 28, or 30 are accessed by it at its earliest convenience.

Turning now to description of the broedcast and reading of messages (also referred to as "tokens") in more detail, only one local control circuit can 'broadcast a message over system bus 40 at one time. When a local control circuit has a message to be broadcast, a request signal is sent by the request function of VME bus requester/arbiter 80 to the arbiter, and if bus 40 is not busy, a grant signal is then sent 9 to the requester by the arbiter. The requester then activates a bus busy signal, and the requesting local control circuit begins data transfer, the drivers in VME bus broadcasccircuit 38 writing a message over system bus 40 to the same addresses of all dual port RAMs 36 via receivers 84. Dual-port PhAM arbier 82 prevents simultaneous access to dual-port RAM 36 by system bus 40 and local bus 34. Both.memory ports are normally disabled and remain so until arbiter 82 grants access, which it only does when requested by a port and.if the other port is not already in use. In case of simultaneous requests for access to dual-port RAM 36, system bus 40 is granted access, and the local port waits until system bus 40 completes its transfer. When access is granted, a data transfer is acknowledged (to the local processor or bus master or both). After acknowledgments have been received from all local control circuits, the broadcasting circuit terminates the data transfer cycle, freeing.system bus 40 for use by other local 'control circuits. The acknowledgments are indicated on a line of system bus 40 via open collector drivers in all local circuits; normal ly the drivers are on, keeping the line in a low state; when a broadcast takes place, each local circuit responds when it has completed data transfer by turning off its driver after a short delay; when all drivers have been turned off, the line rises to the high state.

In order to provide real-time use of the pertinent messages by a local control circuit, e.g., in closed loop control or to provide supervisory messages, local processor 32 is interrupted via local interrupt RAM 86 and local interrupt input port 88 when paeticular message ports are accessed over system bus 40. As mentioned above, local interrupt RAM 86 is loaded during - 10 system initialization by local processor 32 with tag words at addresses corresponding to message ports that are relevant to the operation of a local control circuit; the contents of RAM 86 do not change until specifically reprogrammed by local processor 32. When system bus 40 accesses a message port having a corresponding tag word in local interrupt RAM 86 (an $$active" message port), local interrupt RAM 86 is addressed by the same address lines addressing-dual-port RAM 36. At this time local interrupt RAM 86 is not enabled for writing but is enabled for reading, and the addressed tag word appears on its output data lines, causing a corresponding status bit of an 8-bit addressable latch in local interrupt input part 88 to be set at a "I" simultaneously with the assertion of an interrupt request to interrupt control circuit 56 of local processor 32. The 8-bit addressable latch is directly readable by local processor 32 as an input port to determine which message parts of dual-port RAM 36 have just been accessed. Input part 88 accumulates the status of all active message ports until it has been read by local processor 32, at which time all latched bits are automatically reset to "0". If the number of active message ports exceeds 8, status bits are shared, and message port polling is employed with the interrupts to identify new relevant messages. Having been informed of the arrival of relevant messages, processor-32 reads them as soon as it is convenient.

Dual-port RAMs 36 and broadcast circuits 38 serve as an efficient and general purpose communications mechanism for broadcasting messages to all local Control circuits 22, 24, 26, 28, 30, which need only accebs a small subset of the total number of messages. By isolating system bus 40 from local buses 34, traffic bottle necks across system bus 40 are avoided at the same time that local buses 34 can be efficiently used for data and program associated with the functioning of the local control-element. The message broadcasting thus has no overhead (i.e., special hand-shaking operations) and is transparent to local processors 32 as they carry out their local control, the local processors merely being informed of the arrival in the dual- port RAM 38 of pertinent messages, which can then be read as soon as it is convenient.

r, - 12

Claims

CLAIMS:

Circuitry f or providing interactive control of a plurality of control elements, comprising: a plurality of control elements having specified functions; a plurality of local control circuits adapted to control respective said control elements; each said local control circuit including a processor adapted for operatively controlling operation of said local control circuit and its respective said control element, a local bus connected to said processor and adapted to provide communication within said local control circuit, a message RAM connected to said local bus, and a control element interface connected between said local bus and said respective control element; a system bus connected to said message RAMs in said local control circuits; and a broadcasting circuit adapted for operatively transmitting messages over said system bus to said message RAMs.
2. Control circuitry f or a material -testing load frame, comprising: a plurality of control elements having specified functions, said control elements including an actuator adapted for applying force to a material sample, a load transducer adapted for operatively sensing the load being applied by said actuator, and a strain transducer adapted for operatively sensing strain of said material sample; a plurality of local control circuits adapted for controlling respective said control elements, each said local control circuit including a processor adapted for controlling operation of said local control circuit and its respective said control element, a local bus connected to said processor and adapted to provide communication within said local control circuit, a message RAM connected to said local bus, and a control element interface connected between said local bus and said respective control element; a system bus connected 13 to said message RAMs in said local circuits; and a broadcasting circuit adapted for operatively transmitting messages over said system bus to said message RAMs.
3. Circuitry according to Claim 1 or Claim 2, wherein there are a plurality of broadcasting circuits, each of which is located on a local control circuit.
4. Circuitry according to Claim 3, wherein said broadcasting circuits are adapted to transmit said messages to predetermined memory locations corresponding to the nature of the message.
5. Circuitry according to Claim 4, wherein each said local control circuit includes identifying means adapted to identify the arrival of messages in selected predetermined memory locations.
6. Circuitry according to Claim 5, wherein said identifying means includes an interrupt RAM having addresses corresponding to said predetermined memory locations, said interrupt RAM being connected to be enabled for reading when said message RAM is accessed for writing by said broadcast circuit, said interrupt RAM being loaded with tag words at addresses corresponding to said selected predetermined memory locations.
7. Circuitry according to Claim 6, wherein said identifying means includes means adapted operatively to send an interrupt request to said processor and an addressable latch that has status bits that are set by respective tag words and can be read by said processor.
8. Circuitry according to any of Claims 3 to 7, further comprising a system bus arbiter adapted to limit access to said system bus to one of said plurality of broadcast circuits at one time
9. Circuitry according to Claim 8, wherein said local control circuits include acknowledging means adapted to transmit acknowledgement signals to acknowledge access to said message RAms, and wherein said - 14 broadcast circuits are adapted to cease transmission of a message only after receiving an acknowledgement signal from all local control circuits.
10. Circuitry according to Claim 9, wherein said acknowledging means comprises an acknowledgement line on said system bus and drivers in each local control circuit connected to said acknowledgement line, any said driver being capable of driving said acknowledgement line to one state when turned on, said line going to another state when all said drivers have been turned off, said acknowledgement signal being said another state.
11. Circuitry according to any of Claims 3 to 10, wherein each said local control circuit includes a message RAM arbiter limiting access to said message RAM to either a said broadcast circuit or said processor in said local control circuit at one time.
12. Circuitry according to Claim 1 or any claim appendant thereto, wherein said control elements include at least one actuator and at least one transducer.
13. Circuitry according to Claim 12 or to Claim 2 or any of Claims 3 to 11 when appendant to Claim 2, wherein said transducer is adapted to sense the response of said actuator to a command signal, the processor of said local control circuit for said transducer is programmed operatively to transmit a message indicating said response via its broadcast circuit, and the processor of said local control circuit for said actuator is programmed operatively to read said message and use it in closed loop control of said actuator.
14. Circuitry for providing interactive control of a plurality of control elements, substantially as hereinbefore described with reference to and as shown in the accompanying drawings.
15. Control circuitry for a material-testing load frame, substantially as hereinbefore described with reference to an as shown in the accompanying drawings.
16. A material-testing load frame controlled by circuitry according to Claim 15 or to Claim 2 or any claim appendant thereto.

pub,ls,C:! 1988 c Tile p!ten.:na-'bl. lb.,-ild!r.7. The Pa:en- 0-lice.

Off.Le Sta-A Hcust 66 WC1R 47F Ftr-he: y S.I.S BrLnch, S MLry Cray. C)rpmg:,cn Kent BRIS 3RD pllr.t_,d by MultIplex tec,,uuques ltd. St Ma-y Crpy. Kent. Con. 187.