JPS62217768A - Memory control circuit - Google Patents

Abstract

PURPOSE:To continuously access to different memory areas in the prescribed order by storing at least two pieces of data specifying memory areas and selecting the use of said stored data in the prescribed order. CONSTITUTION:A master MPU sets a start address to an address counter 415 at the time of activating the memory control circuit 4, an address discriminating areas to a bank register 414, data length to be processed to a length counter 412, and command data specifying an action by the circuit 4 to a command register 413. Based on a synchronizing signal generated by a microsequencer 440, the circuit 4 decodes contents in the register 413 by an instruction decoder 430, controls a memory through a bus arbiter 450 or acquires the synchronization of a host CPU with the master MPU. The circuit 4 can continuously access to data in data storage registers 410 and 411 through the use of an inverter logic 416, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application in Industry] The present invention relates to a memory control circuit that controls a memory. In particular, it relates to a memory control circuit of an image processing device.

[Conventional technology]

In image processing devices such as color recording devices controlled by microcomputers (hereinafter abbreviated as MPU), the demand for high-definition output has increased significantly, and as a result, the print heads of color recording devices have also become higher resolution. I came. On the other hand, the amount of information per screen has increased significantly. Therefore, in order to increase the recording speed, the processing time for importing data from the host CPU and generating BK (black) data from Y (yellow), 1M (magenta), and C (cyan) data is increased. The amount has been increasing for a long time. In particular, it is desired to be able to print rask information at high speed with a so-called serial printer, which has a plurality of printing elements arranged vertically in a line and performs printing while operating horizontally with respect to the medium.

To do this, it is necessary to temporarily store the sent rask information in a memory, and after receiving the required amount of rask information, perform data conversion, that is, vertical/horizontal conversion, in accordance with the head structure under the control of software or the like. However, when receiving and converting data using software, the processing time is short when the number of elements in the head is small, so there is no problem, but the number of elements increases, and especially in the case of color data, it is usually
(red), G (green), B (blue) and monochrome data.
Since the amount of data is doubled, the data processing time becomes extremely long.Furthermore, since the ink colors of the print head are Y, M, C, and BK, the processing time is increased because the RGB data must be converted to MMC data. It had the disadvantage of being long.

[Problems to be Solved by the Invention] The present invention has been made in view of the above drawbacks, and includes a function of converting horizontal data to vertical data, a function of converting input color data to corresponding color data, A format conversion function that adapts vertical n-byte image data to the head structure, a memory clear function, a function to discard input data that exceeds the printable range, and a function for when the target memory system is composed of dynamic RAM. The present invention provides a memory control circuit for an image processing device that executes an auto-refresh function at high speed.

[Means for Solving the Problem] As a means for solving this problem, the color recording device 2 shown in FIG. 1 is connected to the host CPU by an interface cable 16, and the interface data width is 8 bits. Or it is composed of 16 bits. The color recording device 2 includes a master MPU 3, a carriage motor 10, a paper feed motor 9, a sub MPU 7, a print head 8, a memory 5, an interface unit 6,
and a memory control circuit 4.

The memory control circuit 4 shown in FIG.
15, bank register 414, and bank selector 41
7, a length counter 412, a data storage register 410, 411, an inverter logic 416, an AND logic 418, a command register 413, an instruction decoder 430, and a bus arbiter 450.
, a micro sequencer 440, and a parallel-to-serial conversion circuit 420
, a bit change 419, and a bit counter 421.

Furthermore, an address counter 415 and a length counter 41
2, a latch is placed in the front stage.

[Operation] In this configuration, image data having a data width of 8 bits or 16 bits transmitted from the host CPU to the interface cable 16 to the interface unit 6 is stored in the memory 5 under the control of the memory control circuit 4. The color recording device 2 is controlled by the master MPU 3 and has the function of converting horizontal data to vertical data and converting input color data to corresponding color data Ii! A
m function, a format conversion function that allows vertical n bytes of image data to correspond to the structure of the head, a memory clear function, and a function that discards input data that exceeds the printable range.
A memory control circuit 4 having an auto-refresh function for when the target memory system is configured with a dynamic RAM converts the input data into print data before and after storing it in the memory, and outputs the data to the print head 8. on the other hand,
The sub MPU 7 controls the carriage motor 10 and paper feed motor 9.

When the memory control circuit 4 is activated, the master MPU 3 sets the start address in the address counter 415, sets the address for determining the area in the bank register 414, sets the data length to be processed in the length counter 412, and sets the data length in the command register. Command data specifying the operation by the memory control circuit 4 is set in 4!3.

The memory control circuit 4 decodes s in the command register 413 (7) with the instruction decoder 430 based on the synchronization signal from the microsequencer 440, and controls the memory 5 through the bus arbiter 450 or synchronizes with the host CPUI and master MPU 3. On the other hand, the data storage register 41o.

Data storage register 411. inverter logic 416
, ANDLogic 418. Parallel to serial conversion circuit 420, bit change 419. Data is converted using the bit counter 421.

Furthermore, an address counter 415 and a length counter 41
The latch in the preceding stage with 2 is used when the memory control circuit 4 repeatedly processes the same data length from the same address.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a color recording device to which an embodiment of the present invention is applied.The color recording device is connected to a host CPU via an interface cable 16, and has an interface data width of 8 bits or 16 bits. has been done. The color recording device 2 has a mask MPU 3 (hereinafter referred to as MMPU 3) that controls the entire carriage motor 10.
and a sub MPU (hereinafter referred to as SM) that controls the paper feed motor 9.
PU 7) and is tightly connected by a wire 12. Furthermore, MMP
U3 is print head 8. Memory 5. It controls the interface unit 6 and memory control circuit 4 (hereinafter referred to as MC4). In this embodiment, the print head 8 has 24 dot elements per head.

FIG. 2 is a block diagram of MC4, which is the gist of this embodiment.
Briefly, an address counter 415 (hereinafter referred to as ADRC415) determines a data transfer destination, a bank register 414 (hereinafter referred to as BR414) for specifying a color memory in the memory configuration shown in FIG. 8, and selects the BR414. A bank selector 417 (hereinafter referred to as BSEL417), a length counter 412 (hereinafter referred to as LC412) that specifies the number of data transfers, and a data storage register 4 for internal work.
10 (hereinafter referred to as DR410), 411 (hereinafter referred to as DR411)
and inverter logic 416 for inverting the data.
(hereinafter referred to as I NV416), the DR410 and DR41
AND logic 418 (hereinafter referred to as A
ND41B), a command register 413 (hereinafter referred to as C0MR413) for setting the operation mode, an instruction decoder 430 (hereinafter referred to as ID430) for analyzing commands, and a bus arbiter 450 (hereinafter referred to as BA450) for synchronizing control signals with external devices. ) and a microsequencer 4 that generates the internal timing necessary for execution processing.
40 (hereinafter referred to as MS440), a parallel-to-serial conversion circuit 420 (hereinafter referred to as PS420) that performs horizontal-vertical conversion, a bit change 419 (hereinafter referred to as BC419), and a bit counter 421 (hereinafter referred to as BC419).
BCNR421) etc. below.

Furthermore, since the MMPU 3 is a 16-bit MPU with 16 bits of data and 23 bits of address, the memory 5 also has a data width of 16 bits. However, the output data 15 of the interface unit 6 is
Depending on the PUI, both 8 bits and 16 bits can be selected by setting the MC4.

Before providing a detailed explanation of the inside of the MCJ, the external specifications of the MC4 and the general specifications of the color recording device 2 will be explained.

Specifications of the color recording device 2> 1. Head configuration... 24 vertical dots/head, Y, M,
C, BK 4 heads 2, Input data format: Rask image format: 8-bit vertical image format: 24-bit vertical image format 3, Color specification format: KGB...RGBBK...・MMC . . . YMCBK The above 2 and 3 will be explained with reference to FIGS. 16 to 19, but in order to simplify the explanation, the input data is limited to the results for one color with an 8-bit width.

FIG. 16 is a diagram comparing the input data and the output result in the raster image format, in which vertical 8-bit input data is regarded as serial data in bytes and output. Control during this format will be explained in detail in the section [Vertical/horizontal conversion (HV mode)].

FIG. 17 is a diagram showing the relationship between input data and output results in a vertical 8-bit image format, and the input data is printed only on dots 1 to B of the head. This means that dots 1 to 8 are not necessarily printed each time one manual data is input, but are usually printed after receiving three input data blocks. That is, the first human-powered data block has dots 1-8, the second human-powered data block has dots 9-16, and the third human-powered data block has dots 1.
7 to 24 are printed.

FIG. 18 shows the relationship between input data and output results in a vertical 24-bit image format, where the input data is interpreted as a byte serial format, and every 3 bytes corresponds to one vertical line of the output results.

Figures 19(A) to 19(D) are examples of color specification formats, and Figure 19(A) is an RGB format, with color data for every N bytes (corresponding to the manual data in Figures 16 to 18). is changed. Similarly, Fig. 19 (B) shows RGBBK
, FIG. 19(C) is MMC, FIG. 19(D) is MMCB
It is in K format. The ink color of the print head is MMC
Since it is BK, formats other than those shown in FIG. 19(D) require color conversion. This is explained in the 20th
In the figure, the RGB format shown in ■ first converts RGB to MMC.
, and then generate BK and a new MMC from the MMC. The reason for creating this new MMC will be described next.

BK Deday is Y = M = C = 1, so when expressing black, if you use Y, M, and C as they are from human data, black will be B.
K.

Since it is printed with all Y, M, and C inks, BK
The Y, M, and C portions of the dots that are printed must be deleted.

Since BK data is added to the RGBBK format (2), only RGB needs to be converted to YMC.

For the YMC format (2), it is only necessary to generate BK data and a new YMC.

As explained above, by supporting the 3FFFI data format and the 4AI color specification mode, it has become compatible with various systems.

<Functions of MC4> MC4 uses DMAC (Direct Memory).
It has the function of reading the interface data 14, writing it to the memory 5, and executing vertical/horizontal conversion and nine-color conversion. An overview of the functions is listed below.

IFR mode...Write interface data to memory CC mode...Execute color conversion (MMC-48K) HV mode...Read interface data,
Immediately, DD mode for vertical/horizontal conversion...reads the interface data,
CD mode that does not write to memory -CDHV mode that writes fixed data in MC4 to memory...IFRI mode that converts fixed data in MC4 vertically and horizontally...HVI mode that writes inverted interface data to memory ...The data obtained by inverting the interface data is converted vertically and horizontally, and each mode will be explained in detail later.

<Description of inside of MC4> As mentioned above, MC4 has a DMAC function. This is a function executed by BA450 in FIG. 2, and stops the operation of MMPU3. This is an operation that must be performed in order for MC4 to start operating.
Furthermore, this function is mostly omitted in the following explanation and timing charts. The operation of BA450 will be explained in detail below.

The MC 4 of this embodiment writes data from the interface unit 6 into the memory 5. Or when reading/writing other various types of memory data, the MMPU 3 must be stopped and the address bus 14b and data bus 14 shown in FIG. 1 must be placed in a free state (tri-state state).

As a means for that purpose, Motorola's 16-bit)-MP
In this color recording apparatus using U (M68000), it is possible to obtain the above state by the method shown in FIG. When the MC4 is ready for operation, the operation is started by an interrupt from the interface unit 6 (not shown).
Or by writing a command from MMPU3 to C0MR413. In FIG. 3, for example, when the MC4 starts operating by writing a command, the MC4 first starts *
This is a response signal from MMPU3 with BR set to LOW*
Wait until BR becomes LOW. *When BR becomes LOW, the address bus 14b and data bus 14 are released, so both addresses and data are placed under the control of the MC4. Therefore, the MC4 starts operating at the same time as *BGA indicating that the operation is being executed is turned LOW. When the operation is finished, MC4 *
Set BGA to HIGH and pass address and data bus management to MMPU3.

[ADRC415... Address counter] A in Figure 2
The DRC415 specifies the address of the target memory, and is composed of a 16-bit counter, and is configured from addresses A1 to A1.
A, has a variable range of 8, ie 64 words.

Since the memory 5 has a data width of 16 bits, the lowest address AO is not normally required, as shown in FIG.
The MC4 is equipped with a counter for Ao. A
The DRC415 has a variable increment amount depending on the settings from the MMPU3, and its biggest feature is that it can set an increment amount of +3 and allows control of both 8 and 16-bit interface data widths, so the same increment amount can be used. However, the increment amount of ADRC 415 is different.

FIG. 21 shows a method of storing input data in the memory 5 when the interface bus width is 8 bits and the input data format is 24 bits vertically.

As shown in FIG. 23, as can be seen from FIG. 17, storing the input data in order in the memory 5 is the easiest form to process including control during printing, so the increment amount of ADRC 415 is If set to +1, the change in address will be n, n+1 . . . if n is initially set. n+2.
n+3... On the other hand, if the input data format is 8 bits vertically, the human input data shown in FIG. 21 is stored in the memory 5 intermittently as shown in FIG. 22. To do this, if the increment amount of the ADRC 415 is set to +3, the output address will be n, n+3°n+6, . . . , and the result will be the same as in FIG. 22. When the increment amount of ADRC415 is set to +1, comparing when the interface bus width is 8 bits and when it is 16 bits, when it is 8 bits, the relationship between the input data in Figure 21 and the memory result in Figure 23 becomes 16 bits. In the case of bits, the human data in Figure 24 and the memory result in Figure 25 are obtained.As can be seen from Figure 25, the address output of ADRC415 is n, n+2.
．． n+4...

Increment amount other than the above description +2. +4...is...
This is to be able to cope with changes in the number of elements in the head used in the device. Note that +3 increments are effective only for 8-bit interfaces, and the configuration is such that when the bus width is 16 bits, the amount is automatically +1 increments.

The above operation will be explained with reference to FIG.

PT810 is "1" when the increment amount is +3, otherwise it is 0", and PO312 is "1" when the increment amount is +1.
BW811 is a signal indicating the interface bus width, and is “1” when it is 8 bits.
, is a signal that becomes "0" when it is 16 bits. 802.8
03 is a binary counter. 801 is a ternary counter, but unlike a normal ternary counter, it reads 0-1→2→0→
Instead of changing as 1..., it changes as 0 → 3 → 2 → 1 → 0-
. . , and a carry signal (not shown) is always supplied to the upper counter (not shown) when counting up from 0 to 3. As a result, if the initial value is O, the lower 3-bit address changes as 0 → 3 → 6 → 9..., and when the initial value is 1, it becomes l-4-7-A..., If the initial value is 2, 2→5-8-B... and so on. Now, when the interface bus width is 8 bits and the amount of change is +3, since PT = 1.8W = 1, the output 816a of the AND gate 816 becomes "1", and the address signal Ao 81
4. A1815 has the output 801 of the ternary counter 801.
a, 801b are output. If the amount of change is +3 and the interface bus width is 16 bits, BW=O, and the AND gate 816 is prohibited.
6a becomes “0”, and from AND gate 813 802
a, 803a are output to outputs 814, 815. or,
POS 12=O, but since it is PT-1, AND gate 808 is enabled, and binary counter 803
is incremented. As a result, when the amount of change is +3 and the interface bus width is 16 bits, the mode is automatically set to +1 and the address signal Ao 814 does not change at all.

Next, when the amount of change is +1, since PT810=O, the AND-OR gate 81
3 selects 802a and 803a. Since BW811=1 when the interface bus width is 8 bits, the operation of binary counters 802 and 803 is as follows.
02 is incremented and AND gate 806 is the carry signal of binary counter 803, so 802
When the binary counter 802 is incremented when a is "1", the binary counter 803 is also incremented at the same time. When BW1311=0, that is! When the width is 6 bits, AND gate 805 is prohibited, so 2
The advance counter 802 does not change, but the AND gate 80
7 is enabled so the binary counter 803 is incremented, resulting in n, n+2 . ...is obtained.

<BR414...Bank register> The color recording device has color memory divided into blocks. Figure 8 is an explanatory diagram of this, and each color represents the address signal A.
It is separated by x 7-A 23. B in Figure 2
R414 consists of four 7-bit registers, each of which can be set independently.

However, the bank for Y must be set to #1, the bank for M must be set to #2, the bank for C must be set to #3, and the bank for B must be set to #4.

The reason for this is that the conversion order is fixed during the color conversion operation.

Although the C0MR413, which will be described later, has bits for selecting BR414, the register numbers pointed to by these bits correspond to the number of BR414. Therefore, MMP
U3 sets all BR414 at the time of initialization, and if you do not change it after that, even if you make a mistake in setting the lower address of Al-Al e when accessing memory using MC4, the address part of BR414 will not change. It has the advantage that the contents of the memory other than the one selected will never be destroyed. Furthermore, by having four BRs 414, even if the lower address register is a single tree, there appear to be four address registers, which is extremely useful.

<C0MR413...Command register> C in Figure 2
The 0MR413 is a 16-bit register, and the MMPU3 writes data to the C0MR413 to instruct the operation mode setting and the operation mode. Its contents include 4 bits for operating mode setting, 2 bits for selecting interface bus width, 2 bits for selecting BR414, and ADRC.
415 bits for setting the increment amount, 4 bits for setting the last current to set the bit position of the target memory during vertical/horizontal conversion, and 1 bit for starting the operation.

The instruction decoding circuit 10430 in FIG. 2 receives the information from the C0MR 413 and starts control according to each operation mode.

<LC412...Length counter> Figure 2 LC41
2 is a 16-bit counter that sets the number of transfers, and is decremented by 1 when one transfer is completed.
When the contents of 2 become all 0, set the end bit 412a to 1"
to notify the ID 430 of the end of the operation.

Although the LC412 is a down counter in the above explanation, the internal circuit of the MC4 uses an up counter in order to simplify the circuit.

Therefore, in order to match the actual setting number and the number of transfers, MC
4 is ID4 when LC412 is selected by MMPU3
30 outputs a chip select signal 823 in FIG.

The chip select signal 823 is sent to the ninth chip by a circuit not shown.
When the inversion control signal 430a is set to "1", the invert circuit 416 inverts the input data 401 and outputs the data 41.
6b to the input terminal of the LC412 in FIG.

The LC 412 takes in the output data 416b inverted by the chip select signal 823. With this circuit, MM
When PU3 writes the number of transfers 1, the output of LC412 is 'F
FFE'. As shown in FIG. 28, the circuit for detecting the end of transfer is an AND gate end state detection gate 821, and all outputs of the LC 412 are connected to the human input terminal. As a result, at the end of the transfer, all inputs are “1”, that is, ′
This is when FFFF' is detected. From this, the above
, FFFE' are set, the LC412 counts up by the count-up signal LCP825 and outputs 'FFFF', which means that the transfer is completed by one increment for the set transfer number 1.

After the power is turned on, the LC controller 412 is in a fail-safe state, so it is required that the transfer is completed, that is, all outputs are "1". However, even if the LC412 has a clear terminal, all outputs become "0" when the LC412 is cleared, so this embodiment does not indicate the transfer end state. Therefore, in this embodiment, by adding the latch 820 shown in FIG. 28, it is possible to enter the transfer end state after power is turned on.

It is the output of the end state detection gate 821.
22 is connected, and the output signal 820a of the latch 820 is connected to one input of the OR gate 822. Since this output signal 820a becomes "1" with the clear signal 824, the output signal 822a of the OR gate 822 also becomes '1', so it is L
No matter what state the contents of C412 are, it indicates the end state. The latch 820 then outputs a signal 820 because the LC412 is in the selected state, that is, when the MMPU3 writes to the LC412, the counter set signal 823 becomes O.
a becomes “O”, and at the same time, 416b is added to LC412.
data is set.

As explained above, a fail-safe circuit can be easily completed by simply inserting one stage of latch, and the LC412 can be an up-counter without a clear terminal, which helps reduce the number of gates when converting this example into an IC. It is clear that it will make a significant contribution.

(Margin below) Each operation mode will be explained below.

[Write interface data to memory] (I
FR mode) This is the most basic operation of the MC4 of this embodiment.

The operation of writing the interface data 15 from the interface unit 6 of FIG. 1 into the memory at the address set in the ADRC 415 inside the MC 4 will be described.

FIG. 5 is a timing chart, and FIG. 6 is an operation flowchart, and the explanation will be based on these.

In both FIG. 5 and FIG. 6, explanation of the portion of returning the MMPU 3 to the stopped state or to the operating state is omitted.

In FIG. 6, in step S61, DRQlol, which is an interrupt signal from the interface unit, goes high.
After detecting that the address bus 14b and data bus 14 are under the control of the MC 4, the contents of the BSEL 417 and ADRC 415 in FIG. 2, that is, the target memory address, are output in step S62. In step S63, the kIFR 106 is turned LOW (in order to subsequently output the data stored in the interface unit 6 to the data bus 14 in FIG. 5). In step S64, if the operation mode is IFH, the process proceeds to step S65. The case when the mode is not IFR, that is, the DD mode will be described later. In step S65, the RW105 signal indicating the read/write status is set to LOW, and the *AS104 indicating the address strobe is also set to LOW.

In step 566, the process branches depending on whether the bit width of the interface data 15 is 8 bits or 16 bits. Now, assuming that the width is 8 bits, the process advances to step S67. In step S7, it is determined whether the valid data on the data bus 14 is the upper 8 bits (Da to Dt5) or the lower 8 bits (D
o~D7) +UDS102 and *LDS10
Outputs 3. Based on these two signals, the memory 5 determines the data to be fetched. At this time, since the ADRC415 only has addresses 1 (A1) to 15 (Az5), a flip-flop for address 0 (AO) (not shown) of the address counter is used to determine the upper and lower order when the data width is 8 bits. *UDS, depending on the value of
*Determine LDS. Step 368 is the final step of the write cycle to memory, *AS104, *U
DS102. *RW105. *All IFR106 are HI
At the same time as changing to GH, address bus 14b and data bus 1
address bus 14 in order to pass the management rights of MMPU 4 to MMPU3.
b. Disconnect the data bus 14 and finish.

Next, we will explain when the interface data bus width is 16 bits, but before that, we will use Figure 4 to explain the case where the interface data bus width is 8 bits/8 bits.
The switching operation for 16-bit width will be explained. When the interface data 15 is 16 bits wide, the data on the data bus 14 is the same as the interface data 15, but when it is 8 bits wide, the data on the interface data 15 is Do-D7 (lower 8 bits) of the data bus 14. Therefore, in order to write to the memory at an odd address (Ao = 1), the same information as the lower 8 bits must be given to the upper 8 bits of the data bus 14.

This is realized in FIG. 4, where the lower 8 bits of the data bus 14 are always supplied to the lower 8 bits of the internal data bus IDo-15 (indicated by 401) of the MC 4 via the buffer 14e. However, while operating in this mode, I
Do-15 is not used inside MC4.

Now, when the data bus width is 8 bits, the data bus 14
The upper 8 bits of the data bus 14 are connected to the B input of the data selector 108, and the lower 8 bits of the data bus 14 are connected to the 8 bits. When the data bus width is 8 bits, BW811 is “
1'', the output Y of the data selector 108 is
Data for A input appears. Since the buffer 14C has a three-state control terminal, the buffer 14C is enabled when BW811 is 1'', so the same information as the lower 8 bits appears in the upper 8 bits of the data bus 14.Similarly, the 16-bit data BWOII when bus width
Since the buffer 14C is "o", the buffer 14C is disabled and has no effect on the upper 8 bits of the data bus 14, and the upper 8 bits of IDo-15 are the upper 8 bits of the data bus 14. The same data is output.

By having this function, which is an embodiment of the present invention, when the memory data bus width is 16 bits, the output interface data 15 of the interface unit 6 in FIG. 1 is composed of 8-bit wide data lines. Also, 16
Even if the data width is bit width, the MMPU 3 only sets the data width of the interface to the MC 4 once and is not concerned with the rest, and the interface data 15 is written to the memory 5 in an orderly manner, so the data management method is becomes very easy.

Next, we will explain the 16-bit data width in IFR mode in the sixth section.
In the figure, steps S81 to S66 are the same as in the case of the 8-bit data width. The difference is that step S66 branches to step S69, and in step S69, since the data width is 16 bits, *ID5102. *This is to set both LDS103 to LOW. The operation is completed by proceeding to step S68 after step S69. FIG. 5 shows the above explanation in terms of timing.

[Impair reading of interface data] (DD mode) This mode is a function that merely reads the data in the interface unit 6, but does not write it anywhere in the memory. To explain using the flowchart in FIG. 6, step S
Steps 61 to 64 are the same as the IFR mode, and step S6
4, the process branches to step S68.

This means that the signals *AS, *UDS, and *LDS are necessary for reading data into the memory 5.

This is an operation mode in which no RW is output, that is, no writing is performed.

This function is very effective in the following cases.

That is, when the host CPUI sends print data beyond the printable range of the color recording device 2 (see Figure 1), the color recording device 2 must discard the excess data, but this operation is handled by the software MMPU 3. It takes a very long time to process with this control.

At this time, if this function is used, the MMPU 3 only needs to set the command and the number of transfers to the MC 4. Therefore, the overhead between reading software interface data and other jobs is significantly reduced.

[Color conversion] (CCD mode) Y (yellow),
BK from three color data of M (magenta) and C (cyan)
The CC mode generates (black) data. Second
7 and 8, but before that, the color conversion generation formula used in this example will be described as follows: BK=Y-M-C Y'=Y-BK M'= M-BK C'=C-BK (Y', M', C' are Y, M after color conversion
, C data).

FIG. 8 shows the structure of storage addresses for each color data in this embodiment. Address signals A17 to A23 separate Y, M, C, and BK, and address signals Ax-Ate
(AO does not exist because the width of the data bus is 16), each word data is accessed. One thing to note about this configuration is that the starting address of each color data (Ax - AX B
(only the range indicated by ) must be the same.

The commands and data sent from MMPU3 to MC4 in FIG. 1 include start address data to ADRC 415 in FIG. 2, number of words transferred to LC 412, B
Bank #1 (Y data memory) to R414, bank #
2 (M data memory), bank #3 (C data memory)
, setting the data of bank #4 (BK day memory),
Finally, there is a color conversion command to C0MR413.

After receiving the color conversion command, the MC4 transfers the address bus 14b,
When the data bus 14 comes under the control of the MC 4, color conversion starts. FIG. 7 is a timing chart showing the execution state, and AX-A23 is an address signal, especially ALT-
A23 is the bank address of the upper 7 bits, and Ax7-
#n in A23 is the bank number. This indicates that data corresponding to bank #n set in the BR414 is output, and n of A1-Ax6 is ADR, C
The data set in 415 is shown. Also, data Do −
15 I or 0 indicates the direction of data, ■ indicates the transfer direction from the memory 5 to the MC4, and 0 indicates the transfer direction from the MC4 to the memory 5. *AS, *UDS, *LDS, and RW are all signals output by the MC 4, and the memory 5 uses these signals to control data input or output.

The color conversion procedure for one word will be explained step by step with reference to FIG. In step S71, the address outputs bank #1 (Y data memory 501 in FIG. 8 is selected),
The Y data is taken into the DR410 in FIG. Step S7
2, outputs puncture #2 (M data memory 5 in Figure 8).
o2) and import the M data into the DR411 in FIG. In step S73, the AND circuit 41 is internally operated by the MC4.
8, the 7nd of DR410 and DR411 is taken, and the ANDed data is taken into DR411. In step S74, puncture #3 is taken into the output (C data memory 503 in FIG. 8) L, DR 410. Step S7
5, the operation is exactly the same as step S73, but as a result, Y*M*C, that is, BK data remains in the DR 411. In step S76, the puncture #4 (BK date 504 in FIG. 8) is output and written into the memory.
In step S77, new Y and M are set.

As a preliminary preparation for generating C data, the BK data is inverted and rewritten to the DR 411.

This means that the ID430 sets the inversion signal 430a in FIG.
” and supplies it to the INV416, the data on the internal data bus 401 is inverted and becomes the input to the DR411. This is explained in FIG. 9. In the case of non-inversion, the inversion signal 430a is “0”. Therefore, the internal data 401 is supplied to the DR4!1 without being inverted, and at the time of inversion, the inversion signal 430a becomes "1", so the internal data 401 is inverted and supplied to the DR411. The signal is easily obtained.In step 578, the Y data is loaded into the DR 410.

In step S79, the AND signal of DR410 and DR411, that is, new Y data, is written to the Y data memory 501.In step S80, M data is taken into DR410.In step S81, DR410 and DR411
In step S82, the new M data is written to the M data memory 502, the C data is written to the DR410.
In step S83, DR410 and DR4
11 AND signal, ie, new C data, is written into the C data memory 503. At this step, the color change of one word is completed, so add 1 to ADRC415, and then add 1 to LC41.
Subtract 2 by 1. As a result, if the content of LC412 is not zero, the next word conversion is executed as shown in FIG. 7, and if it is zero, the process ends.

As described above, according to this embodiment, the color conversion of one word (two bytes) is performed without interruption to the memory 5, so it can be seen that it can be executed much faster than conversion by software.

[Vertical/horizontal conversion] (HV mode) This mode is used when the data format from the host CPUI is a raster image format, as shown in Figure 10 (a).
) to (C) are diagrams comparing input data from the host CPU 1 and the contents of the memory after conversion. The input data (output data from the host CPUI) when the interface bus width is 8 bits is shown in FIG. 10(a), and the contents of the memory 5 after execution of this mode are shown in FIG. 10(b).

It is shown in (C). In both FIGS. 10(b) and 10(c), the shaded areas indicate that the contents have not changed at all from before the execution of this mode. FIG. 10(b) is the result of executing MSB first conversion, and FIG. 10(C) is the result of executing LSB first conversion, and the differences between the two will be described later.

Here, the HV mode will be explained with reference to FIG. 2, FIG. 11, and FIG. N12 on the premise of MSB (D?) optical conversion. Note that the part for importing the interface data 15 is omitted, and it is assumed that the data in FIG. 10(a) is stored in the DR 410.

In Figure 11, BCNR421 is an octal binary counter,
PSMX of PS420 is an 8→1 multiplexer, Y is a positive logic output, BCSL of BC419 is a 4→16 data selector, and BCA to BCA32 are AND gates.

Explaining according to Fig. 12, the address at the start of operation is m
, LD=1 (indicating MSB first conversion), when the bit designation signal 430b of the target memory in FIG. , DR410 specifies memory Di in the example of FIG. 10(b).

In step 5121, the data at address m is DR
411.

In step 5122, the first bit obtained by parallel-to-serial conversion of the output of DR411 appears at 420a in FIG.
Replace the output of 0 with 4108 glue in Figure 11 and get 410
Data other than OX of a is written to the memory at address m without being changed at all. In the above operation, BCNR421 is all 0''
', and since LD = 1, PSMX inputs A and B
, C are all “1”, so the output Y4 of PSMX
Dl of the output 411a of the DR 411 is output to 20a. On the other hand, the output of BCSL is when the input is A-1 and B-C=D
-0, so only BC3LI is “O” and everything else is “1”, so the output 410a of DRl 40 is B
CAI, BCA5°BCA9. . . . Since the BCA 31 is enabled, the same data as 410a is output to the internal data bus 401 except for Dl. BCA3. B.C.
Regarding A4, since BCAL1=O, BCA3 is disabled and BCA4 is enabled, so the signal of 420a, that is, the M SoB of 411a, is transferred to the internal data bus 40.
1 is output. This results in the same result as the address m in FIG. 10(b).

At the end of this step BCNR421 and ADRC41
Prepare for the next step by adding 1 to 5.

As a result, the address Al - Al s is m+1, B
Output of CNR421 421a=1, 421b=421c
=O1, that is, inputs A and B of PSMX.

For C, A=O, B=C=1.

In step 123, the data at the address indicated by A, -Al6 is taken into the DR 411.

Step! 24 is the same as step 122, except that the content of the PSMX output Y420a is selected by the PSMX inputs A, B, and C (D6 is selected in step 124).

Do the above in odd steps (121, 123゜125-)
, the same operations as the even number steps (122, 124°, 126, . . . ) are repeated. In step 5136, LC421
Since the operation of subtracting 1 by 1 is added and the conversion is completed in step 136, the operation of the MC4 itself is completed and the management of the address bus 14b and data bus 14 is handed over to the MNPU3.

The above explanation is based on the data stored in DR411.
Although the code is converted with B (Dl) at the beginning, the feature of this embodiment is that it is provided with a mode in which conversion is performed with LSB (Do) at the beginning.

To implement this method, when sending a command to MMPU 3 or rubber MC 4, a switching command for MSB/LSB (or by an external terminal of MC 4) is provided, so that the LD signal shown in FIG. By setting it to “0” in the previous case, it becomes the selection input terminal A of PSMX.

B and C become D by inverting and non-inverting the output of BCNR421.
It is determined whether the selections are made in order starting from 7 or if it is DO.

By providing this function, there are two types of raster formats per host CPU, so the host CPU
This has the advantage of being easily selectable as a processing method within I.

Further, in the above description, the interface bus width was 8 bits, but a feature of this embodiment is that a 16-bit bus width can also be selected (see IFR mode). Although the specific means are not shown, taking FIG. 11 as an example, BCN
Make R421 a 4-bit counter and make PSMX the first
This is achieved by changing the 8→1 multiplexer in Figure 1 to 16→1 multiplexer.

As described above, according to this embodiment, vertical and horizontal conversion of 1 byte, 8 bits can be performed in a short time of 16 steps. now,
If one memory cycle is 250ns, then 250nsX
It ends in 1B=4ns.

[Writing fixed data] (CD, CDHV%-de) This example is simple and operates as a MAC, but the D
It has functions that MAC does not have.

These are fixed data write modes, namely CD mode and CDHV mode.

In this mode, when data is written to DR411 in MCJ, data in DR411 is continuously transferred to memory 5 for the number of transfers.
This is the operation of writing to.

The CD mode has exactly the same operation as the IF trap mode and the CDHV mode except for the following points.

The difference is that the target conversion data is data written to DR411 in CD and CDHV modes, and interface data in IFR and HV modes.
In the HV mode, the number of transfers set in the LC 412 is continuously executed. This is explained in Figure 13 (
a).

(b) and Fig. 13 (a) are explanatory diagrams of IFR and HV modes, where DRQ is an interrupt signal from the interface unit 6, and when MC4 detects DRQ, it becomes a management light for the address data bus, and after completing the specified processing. One byte (or one word) is processed in one process when the bus management right is passed to the MMPU 3.

FIG. 13(b) is an explanatory diagram of the CD and CDHV modes.
When MPU3 writes a command to MC4, MC4
performs continuous processing for the amount set in the LC 412. Therefore, if the number of transfers is large, it will take a long time until the MMPU 3 becomes operational.

14(a) and 14(b) show the contents of the memory 5 after executing the CD and CDVH modes, respectively.
(b) It is very effective when used to clear the memory as shown in the figure. To write a staggered pattern as shown in Fig. 15 to the memory 5, 1. Set the nearest start address to n. 2. Set the increment amount of the near address counter to +2. 3. Set the transfer number N to the length counter. 4. Set the DR411.゛
Set 1010101010101010° 5: Send CD command: (MC4 executes CD mode) 6: Set start address to n+1 7: Set address counter increment to +2 8: Set transfer number N to length counter “9 :DR411 to X'0101
Setting 010101010101 10: Sending a CD command (execution of CD mode) This has the advantage of being able to create a staggered pattern at high speed.

[Data inversion] (IFRI, 1 (Vl-1--do)) Both modes perform the same operation as IFR and HV modes, but this mode differs from IFR and HV modes in that interface data !5 is inverted and used. .

To explain the I FRI mode in Figures 9 and 29,
In the IFRI mode, the signal 430a in FIG. 9 is set to 1''.
and import the interface data 15 into the DR441. Since the signal 430a is 1", the inverted data of the internal data bus 401 is stored in the DR411. Next, when *IFR in FIG. 29 is set to "1", the data bus 401 becomes floating, so the MC4 is The contents of DR411 are output to the data bus 14, and control signals *UDS, *LDS, *AS, and RW are output to the memory 5, and the process ends.

In the HVI mode, the only difference from the HV mode is that 4038 in FIG. 9 is set to 1'' and the inverted interface data 15 is taken into the DR411, as in the IFRI mode, and everything else is the same as the HV mode. .

The advantage of the wood mode is effective when converting RGB data to MMC data. This is shown in Figures 19 and 30.
To explain using figures, Fig. 30 (A) is different from Fig. 19 (
The data format of A) and FIG. 30 (B) explain an example of the data format of FIG. 19 (C). Since the data format of FIG. 9M is bank #1 in bank #1.
2, C may be stored in bank #3. This is the 30th
As explained in Figure (B), when setting the IFR mode, select the link number #1. You can do it in the order of #2 and #3. On the other hand, the data format in Figure 19 (A) is RGB.
Since it is a format, it is necessary to convert it to MMC. For this purpose, a conversion expressed by the formula Ys-notB M=notG C=notR is performed. This is achieved in the I FRI or HBI mode, and as explained in A in Figure 30, the first data block is R, so the bank #
3, next is M, so select bank #2, and last is B, so select bank #1. MMPU3 can execute the software related to color conversion by commands, addresses, etc. for MC4. It is very efficient because it only requires setting the number of transfers.

After this, the aforementioned CC mode is used to convert YMC to YMCBK.

Auto refresh function> If the printable area of this color recording device is 8 inches and the horizontal dot resolution is 200 dpi (dots/inch), the memory capacity required for one line is 8 (inches) x 2.
00 (dpi) x 24 (element/head) x 4
(Number of heads)=153,600 bits, and if this is expressed in number of bytes, it becomes 153,600÷8=19.2KB. With this level of capacity, it is natural to use static RAM, but in another application example, assuming a device with a printable area of 15 inches, a dot resolution of 400 dpi, and 128 elements/head, the memory capacity would be 384 KB. Therefore, dynamic RAM can be considered as the memory to be used. Dynamic RAM has the disadvantage that memory contents change unless it is refreshed periodically. The refresh circuit creates a refresh signal under the control of the MMPU 3, or detects free time inside the memory 5 between accesses from the MMPU 3 and creates a refresh signal. However, in this embodiment, especially in color conversion, the color conversion is executed within the cycle time limit of the memory 5, and since it is impossible for the MMPU 3 to interrupt the execution while it is being executed, there is a possibility that refreshing will not be possible. I'm coming.

To compensate for this drawback, the MC4 is provided with an external terminal for an AR multiplier signal (not shown), and when the ARIR number is 1'', the CC-
Auto-refresh is executed only for T--, CD, and CDHV-[--. The reason why auto-refresh is not executed in modes other than the above is that the first
In FIG. 3(a), the time during which the MC4 manages the address bus 14b and the data bus 14 is less than 1 μs, and the address bus 14b and the desta bus 1 are
The control in step 4 is to temporarily return to the MMPU3.

For Soleni, CC, CD, CDHVMoF is the 13th
As shown in Figure (b), for a long time the address bus 14b
This is because the MC4 manages the data bus 14. This will be explained using FIG. 7 and FIG. 31, taking the CC mode as an example.

FIG. 7 shows an example when auto-refresh is not executed, and step n in the CC mode is a repetition of steps 71 to 83.

On the other hand, when auto-refresh is executed, one cycle of dummy steps is inserted between step S83 and the next step S71, as explained in FIG. 31, and at this time a refresh pulse *RF is output. At this time *AS, *LD
S.

All RSs are Bi. The reason that the AL-A23 in FIG. 31 outputs exactly the same signal as in step S83 is because the MC4 does not have an address counter for refreshing. Therefore, when the memory 5 receives kRF, it performs refresh using its own address counter.

(LC latch, ADRC latch) MM when storing data in the MMC data format shown in Figure 19 (C) in the memory 5 using IFR mode
The outline of the commands etc. that the PU3 sends to the MC4 has already been described in Figure 30 (B), but to explain this in more detail, there are three processes: address counter setting, length counter setting, and command setting. The IFR mode is executed by repeating it three times, but as explained in Figure 19 (C), the length counter has the same length data for all Y, M, and C, and the contents of the address counter are also the same. Because data must be stored from the same address for color conversion processing, it is necessary to set the same data. Therefore, LC412,AD
If a latch is provided in the data input section of RC415, ADRC
415 and the settings for the LC 412 only need to be done once, which greatly simplifies the processing on the MMPU 3 side. This is explained in FIGS. 32 and 33. LC412, AD
Since both RC415s differ only in function and are the same in terms of data settings, only the LC412 section will be explained. FIG. 33(A) is an address assignment table for registers and counters before a latch is provided, and for convenience of explanation, $1 is left blank. When setting data to LC412 now, MM
When PtJ3 writes to address xxxX2, the data at that time is stored in LC412.

FIG. 33(B) is an address assignment table when a latch is provided, and although it is not changed from FIG. 33(A), the circuit is different. That is, a latch 831 is provided in front of the input section of the LC 412 in FIG.
Take in b. When MMPU3 writes data to address xxxx2 in FIG. 33(B) in order to set data in LC412, the clock signal 833 of latch 831 in FIG. 32 becomes 1", and latch 831 writes data 416.
Take in b. Subsequently, MMPU3 is Co) JR41
When data is written to 3, the signal 834 becomes “0” and the LC
412 is a latch 831 and takes in data. With this circuit, it is only necessary to set data to ADRC 415, L, and C 412 once before step 5311 in FIG. 30(B), and it is not necessary in steps 5312 and 5313.

It is obvious that the load on the MMPU 3 can be further reduced by implementing the circuit described above.

However, when the input data format is raster image data, YMC format, and 1 color data is 10
When it is 0 byte, as explained in FIG. 34, from receiving the manual data to printing, in step 5341, the ADRC 415, that is, the start address setting is O in this example, and the LC 412 is set to 100 bytes for 1 color data. Since it is a byte, set it to 100.

In step 5342, the vertical/horizontal conversion HV mode is repeated 72 times. The color specification format for this is Y.

2 because it is M, C and the number of head elements is 24.
Since data is received 4 times, the number of vertical and horizontal conversions is 3X24.
This is because it becomes -72.

In step 5343, the address and the value of LC412 are reset to execute the color conversion CC mode. ADRC
415 can be 0, but LC412 has input data of 100.
As explained in Figures 10(a) and (b), the byte is converted horizontally and vertically, so it is stored in the memory multiplied by eight in the horizontal direction, so 100X8=800,800 is stored in the LC412.
Set to .

In step 5344, the CC mode execution step 53
In step 45, the process for one printing is completed after printing is executed, and the process proceeds to step 53.
41, but at step 5341, ADRC4
15. Specified values must be set for LC412.

A circuit devised to improve this point is shown in Figure 35.
As a result, after the first printing is completed in FIG. 34, instead of returning to step 5341, the process returns to step 5342, as shown by the dotted line. Due to this, MMPU
The software in No. 3 is further simplified. The method will be explained below.

Figure 33 (C) is an address allocation table when the improved plan is implemented. The difference from Figures 33 (A) and (B) is that $1 is the command register, $4 is the length latch, and $5 is the address latch. This is the point I made.

FIG. 35 shows an example of a circuit, in which the latch 831 in FIG. 32 is changed to a latch with a tri-state buffer, and the circuit changes from FIG. 32 to FIG. 35 by adding a tri-state buffer 830.

When the MMPU 3 selects the length counter of $2 in FIG.
0 is enabled and the buffer part of the latch 831 is disabled, so the internal bus 416B appears at the input part of the LC412, and at the same time the signal 823 becomes "0", so the output 835a of the OR gate 835 also becomes "O". , LC 412 receives the same data as 416b. When the MMPU 3 selects the length latch of $4, the signal 833 becomes "1" and the latch 831 takes in the data of 416b. In order to transfer the data captured in the latch 831 to the LC 412, the MMPU 3 only needs to select the $1 command register. At this time, the signal 832 is “
1'', the buffer 830 is disabled, and the output of the latch 831 is enabled, so the contents of the latch 831 appear in 830a, and as a result, the same data as the contents of the latch 831 is loaded into the LC 412. It is shown in FIG.

The operation of FIG. 34 by this circuit is as follows: In step 5341, the start address is set in the $5 address latch, and the number of transfers, 100, is set in the $4 length latch.

In step 5342, the operation of setting the HV command in the $1 command register is repeated 72 times.

In step 5343, the start address is set in the address counter of $3, and the number of transfers, 800, is set in the length counter of $2.

In step 5344, CC is stored in the command register of $O.
Set the mode and execute.

In step 5345, printing is executed, and after completion, step 5
Return to 342.

In the above explanation, there are two C0MRs 413, but in reality there is only one tree of registers, and they are designed to operate differently depending on the address.

As described above, the present invention has the effect of greatly simplifying the MPU software by applying it to a color recording device in particular, and furthermore, it has a large capacity because it executes interface data import, color conversion, vertical/horizontal conversion, etc. at ultra-high speed. A color recording device with high throughput can be realized even with data of

(The following is a blank space) [Effects of the Invention] According to the present invention, it is possible to provide a memory control circuit that continuously accesses different designated memory areas without communicating with the main control device.

(Margin below)

[Brief explanation of drawings]

Figure 1 is a block diagram of the color recording device, Figure 2 is a block diagram of the memory control circuit, Figure 3 is a timing chart of the use of the memory control circuit data bus and address bus, and Figure 4 is 8-bit width/16-bit width. Switching circuit diagram, Figure 5 is a timing chart of IFR mode, Figure 6 is a flowchart of IFR mode, Figure 7 is a timing chart of CCD mode, Figure 8 is an addressing diagram of the memory control circuit, and Figure 9 is the inverter logic. Circuit diagram, Figures 10 (a) to (c) are HV mode explanatory diagrams, Figure 11
The figure shows an HV conversion circuit diagram, Figure 12 is a timing chart of HV mode, Figure 13 (a) is a diagram explaining IFR and HV mode, Figure 13 (b) is a diagram explaining CD and CD HV mode, Figure 14 (a) ) is a memory status diagram after executing the CD mode, Figure 14(b) is a memory status diagram after executing the CDVI (mode), Figure 15 is a staggered pattern formation status diagram, and Figure 16 is the input data and output in Leicester format. A comparison diagram of the results. Figure 17 is a comparison diagram of human input data and output results in vertical 8-bit image format. Figure 18 is a comparison diagram of manual input data and output results in vertical 24-bit image format. Figure 19 (A) ) to (D) are color specification format side ports, Figure 20 is a color conversion explanation diagram, Figure 21 is an 8-bit width input data diagram, and Figure 22 is a vertical 8-bit width diagram.
Fig. 23 is a storage state diagram when formatting 24 bits vertically with 8-bit width input; Fig. 24 is a diagram of input data with a 16-bit width; Fig. 25 shows an 8-bit width input data diagram.
Storage state diagram for vertical 24-bit format with bit width input, Figure 26 is a partial circuit diagram of the address counter, Figure 27 is an address designation diagram of the memory control circuit, Figure 28 is a length counter circuit diagram, and Figure 29 is a diagram of the address counter. Timing chart of IFRI mode, Figure 30 (A) is flowchart of IFRI mode, Figure 30 (B) is flowchart of IFR mode, Figure 31 is timing chart of auto-refresh, Figure 32 is latch circuit of length counter. Figures 33(A) to 33(C) are explanatory diagrams of commands to the memory control circuit, Figure 34 is a flowchart of the mask MPU, Figure 35 is a control circuit diagram of the length counter and latch, and Figure 36 is the length counter and latch control circuit diagram. In the figure, 1... host CPU, 2... curler recording device, 3... master MPU, 4... memory control circuit,
5...Memory, 6...Interface unit,
7...Sub MPU, 8...Print head, 9...Paper feed motor, 10...Carriage motor, 410°4
11...Data storage register, 412...Length counter, 413...Command register, 414...
・Bank register, 415...address counter, 4
16... Inverter logic, 417... Bank selector, 418... AND logic, 419... Bit change, 420... Parallel to serial conversion circuit, 421...
・Bit counter, 430... Instruction decoder, 440... Micro sequencer, 450...
・It is a bus arbiter. Patent applicant: Canon Co., Ltd. Figure 5 Figure 9 Figure 10 (a) Figure 10 (b) To Figure 1o (c) Figure 13 (()) Figure 13 (b) Figure 17 Printed Eka thread Yoshika Old Map Print 1 Result 19th Prisoner (A) 19th Country (B) 19th Prisoner (C) Fig. 19 (D) Fig. 20 Fig. 21 Fig. 22 Fig. 23 Cause 24th Ward 3011m (A) 30th rIA (8) o
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Claims (1)

[Claims] (1) In a memory control circuit that controls a memory using a direct memory access method, there is provided storage means for storing at least two pieces of data specifying a memory area, and a memory control circuit for controlling the use of the at least two pieces of data stored in the storage means in a predetermined manner. What is claimed is: 1. A memory control circuit comprising: selection means for sequentially selecting different memory areas, and sequentially accessing different memory areas in a predetermined order.