JPS62219295A - Memory control circuit - Google Patents

Abstract

PURPOSE:To provide direct memory access type memory control with a complicate function by providing an output means which outputs a refresh pulse in case a volatile memory is occupied by a control which lasts beyond a specified length of time. CONSTITUTION:A master MPU 3 sets a start address in an address counter 41 and an address for discriminating an area in a bank register 414, and also sets the length of data to be processed in a length counter 412 and a command data for specifying the operation of a memory control circuit 4 in a command register 413 at the time of a memory control circuit 4 is started. The memory control circuit 4 decodes the contents of the command register 413 by an instruction decoder 430 based on a synchronizing signal from a microsequence 440 to convert data while controlling a memory 5 and synchronizing a host CPU 1 and the master MPU 3 with each other through a bus arbiter 450.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control circuit that controls a memory. In particular, it relates to a memory control circuit of an image processing device.

[Prior Art] In image processing devices such as color recording devices controlled by microcomputers (hereinafter abbreviated as MPU), the demand for high-definition output has increased significantly, and with this, the print heads of color recording devices have also improved. It has become high resolution. On the other hand, the amount of information per screen has increased significantly. Therefore, in order to increase the recording speed, the processing time for importing data from the host CPU and generating BK (black) data from Y (yellow), 1M (magenta), and C (cyan) data is increased. The amount has been increasing for a long time. In particular, it is desired to be able to print rask information at high speed with a so-called serial printer, which has a plurality of printing elements arranged vertically in a line and performs printing while operating horizontally with respect to the medium.

To do this, it is necessary to temporarily store the sent rask information in a memory, and after receiving the required amount of rask information, perform data conversion, that is, vertical/horizontal conversion, in accordance with the head structure under the control of software or the like. However, when receiving and converting data using software, the processing time is short when the number of elements in the head is small, so there is no problem, but the number of elements increases, and especially in the case of color data, it is usually
(red), G (green), B (blue) and monochrome data.
Since the amount of data is doubled, the data processing time becomes extremely long.Furthermore, since the ink colors of the print head are Y, M, C, and BK, the processing time is further increased because the RGB data must be converted to YMC data. It had the disadvantage of being long.

[Problems to be Solved by the Invention] The present invention has been made in view of the above drawbacks, and includes a function of converting horizontal data to vertical data, a function of converting input color data to corresponding color data, A format conversion function that matches vertical n-byte image data to the head structure, a memory clear function, a function to discard input data that exceeds the printable range, and a function for when the target memory system is composed of dynamic RAM. The present invention provides a method control circuit for an image processing apparatus that executes an auto-refresh function at high speed.

[Means for Solving the Problem] As a means for solving this problem, the color recording device 2 shown in FIG. 1 is connected to the host CPU by an interface cable 16, and the interface data width is 8 bits. Or it is composed of 16 bits. The color recording device 2 includes a master MPU 3, a carriage motor 10, a paper feed motor 9, a sub MPU 7, a print head 8, a memory 5, an interface unit 6,
and a memory control circuit 4.

The memory control circuit 4 shown in FIG.
15, bank register 414, and bank selector 41
7, length counter 412, data storage registers 410, 411, inverter logic 416, AND logic 418, command register 413, instruction decoder 430, and bus arbiter 450.
, a micro sequencer 440, and a parallel-to-serial conversion circuit 420
, a bit change 419, and a bit counter 421.

Furthermore, an address counter 415 and a length counter 41
2, a latch is placed in the front stage.

[Operation] In this configuration, image data having a data width of 8 bits or 16 bits transmitted from the host CPU to the interface cable 16 to the interface unit 6 is stored in the memory 5 under the control of the memory control circuit 4. The color recording device 2 is controlled by the master MPU 3 and has a function of converting horizontal data to vertical data, a function of converting input color data to corresponding color data, and making the image data of vertical n bytes correspond to the structure of the head. The memory control circuit 4 has a format conversion function, a memory clear function, a function to discard input data exceeding the printable range, and an auto refresh function when the target memory system is configured with dynamic RAM. Before and after storage, the input data is converted into print data and output to the print head 8. On the other hand, sub M
The carriage motor 10 and paper feed motor 9 are controlled by the PU 7.

When the memory control circuit 4 is activated, the mask MPυ3 sets the start address in the address counter 415, sets the address for determining the area in the bank register 414, sets the data length to be processed in the length counter 412, and sets the data length in the command register 413. memory control circuit 4
Sets command data that specifies the operation. The memory control circuit 4 decodes the contents of the command register 413 with an instruction decoder 430 based on the synchronization signal from the microsequencer 440, and controls the memory 5 through the path arbiter 450 or the host CPU.
While synchronizing with the UI and the master MPU 3, the data storage register 41o.

Data storage register 411. inverter logic 416
, ANDLogic 418. Parallel to serial conversion circuit 420, pit change 419. Data is converted using the bit counter 421.

Furthermore, an address counter 415 and a length counter 41
The latch in the preceding stage with 2 is used when the memory control circuit 4 repeatedly processes the same data length from the same address.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a color recording device to which an embodiment of the present invention is applied. The color recording device is connected to a host CPU via an interface cable 16, and the interface data width is configured to be 8 bits or 16 bits. has been done. The color recording device 2 has a mask MPU 3 (hereinafter referred to as MMPU 3) that controls the entire carriage motor 10.
and a sub MPU 7 (hereinafter referred to as S) that controls the paper feed motor 9.
It is tightly connected to the MPU 7) through a wire 12. Furthermore, MM
PU3 is the print head 8. Memory 5. The interface unit 6 and memory control circuit 4 (hereinafter referred to as MC4) are connected to i! l
Do I#. In this embodiment, the print head 8 has 24 print heads per head.
Targeted for dot elements.

FIG. 2 is a block diagram of MC4, which is the gist of this embodiment.
Briefly, an address counter 415 (hereinafter referred to as ADRC415) determines a data transfer destination, a bank register 414 (hereinafter referred to as BR414) for specifying a color memory in the memory configuration shown in FIG. 8, and selects the BR414. A bank selector 41 (hereinafter referred to as BSEL417), a length counter 412 (hereinafter referred to as LC412) that specifies the number of data transfers, and a data storage register 4 for internal work.
10 (hereinafter referred to as DR410), 411 (hereinafter referred to as DR411)
and inverter logic 416 for inverting the data.
(hereinafter referred to as INV416), the DR410 and DR411
AND logic 418 (hereinafter referred to as AN
D418), a command register 413 (hereinafter referred to as C0MR413) for setting the operation mode, an instruction decoder 430 (hereinafter referred to as It) 430) for analyzing commands, and a path arbiter 450 (hereinafter referred to as It) for synchronizing control signals with external devices. BA450) and a microsequencer 4 that generates the internal timing necessary for execution processing.
40 (hereinafter referred to as MS440), a parallel-to-serial conversion circuit 420 (hereinafter referred to as PS420) that performs horizontal-vertical conversion, a bit change 419 (hereinafter referred to as BC419), and a bit counter 421 (hereinafter referred to as BC419).
BCNR421) etc. below.

Furthermore, since the MMPU 3 is a 16-bit MPU with 16 bits of data and 23 bits of address, the memory 5 also has a data width of 16 bits. However, the output data 15 of the interface unit 6 is
Depending on the PUI, both 8 bits and 16 bits can be selected by setting the MC4.

Before providing a detailed explanation of the inside of the MCJ, the external specifications of the MC4 and the general specifications of the color recording device 2 will be explained.

Specifications of the color recording device 2> 1. Head configuration... 24 vertical dots/head, Y, M,
C, BK 4 heads 2, Input data format... Rask image format... Vertical 8-bit image format... Vertical 24-bit image format 3, Color specification format -RGB...-RGBBK...YMC ・- MMCB The above 2 and 3 will be explained with reference to FIGS. 16 to 19, but in order to simplify the explanation, the input data is limited to the results for one color with an 8-bit width.

FIG. 16 is a diagram comparing the input data and the output result in the rask image format, in which vertical 8-bit human data is output as serial data in bytes. Control during this format will be explained in detail in the section [Vertical/horizontal conversion (HV mode)].

FIG. 17 is a diagram showing the relationship between input data and output results in a vertical 8-bit image format, and the input data is printed only on dots 1 to 8 of the head. This means that dots 1 to 8 are not always printed each time data is input by one person, but usually three blocks of input data are received and then printed. That is, the first input data block corresponds to dots 1 to 8, the second input data block corresponds to dots 9 to 16, and the third input data block corresponds to dots 1.
7 to 24 are printed.

FIG. 18 shows the relationship between input data and output results in a vertical 24-bit image format, where the input data is interpreted as a byte serial format, and every 3 bytes corresponds to one vertical line of the output results.

Figures 19 (A) to (D) are examples of color specification formats, and Figure 19 (A) is an RGB format, where color data is provided every N bytes (corresponding to the input data in Figures 16 to 18). is changed. Similarly, Fig. 19 CB) is RGBBK
, Fig. 19(C) is MMC, Fig. 19(D) is YMCB
It is in K format. The ink color of the print head is YM'
Since it is CBK, formats other than those shown in FIG. 19(D) require color conversion. The second thing to explain this is
In Figure 0, the RGB format shown in ■ is first converted from RGB to MM.
Convert to C, then generate BK and new MMC from MMC. The reason for creating this new YMC will be described below. BK data is Y-M=C=1, so to express black, if you use Y, M, and C as input data, black will be B.
K.

Since it is printed with all Y, M, and C inks, BK
The Y, M, and C portions of the dots that are printed must be deleted.

Since BK data is added to the RGBBK format (2), only RGB needs to be converted to YMC.

For the MMC format (2), it is only necessary to generate BK data and a new MMC.

As explained above, there are three types of data formats and 4f
f! By supporting various color specification modes, it has become compatible with various systems.

<Functions of MC4> MC4 uses DMAC (Direct Memory).
It has the function of reading the interface data 14, writing it to the memory 5, and executing vertical/horizontal conversion and nine-color conversion. An overview of the functions is listed below.

IFR mode...Writes interface data to memory CC mode...Executes color conversion (YMC→BK) HV mode...Reads interface data,
Immediately, DD mode for vertical/horizontal conversion...reads the interface data,
CD mode that does not write to memory - CDHV mode that writes fixed data in MCJ to memory - IFRI mode that converts fixed data in MC4 vertically and horizontally - HVI mode that writes inverted interface data to memory ...The data obtained by inverting the interface data is converted vertically and horizontally, and each mode will be explained in detail later.

<Description of inside of MC4> As mentioned above, MC4 has a DMAC function. This is a function executed by BA450 in FIG. 2, and stops the operation of MMPU3. This is an operation that must be performed in order for MC4 to start operating.
Furthermore, this function is mostly omitted in the following explanation and timing charts. The operation of BA450 will be explained in detail below.

When the MC 4 of this embodiment writes data from the interface unit 6 to the memory 5 or reads/writes various other types of memory data, the MMPU 3 is stopped and the address bus 14b and data bus 14 of FIG. must be brought into a free state (tristate state).

As a means of achieving this, we use a 16-bit MPU manufactured by Motorola.
(M68000), this color recording device uses
It is possible to obtain said state by the method shown in FIG. When the MC4 is ready for operation, the operation is started by an interrupt from the interface unit 6 (not shown) or by writing a command from the MMPU3 to the C0MR413. In FIG. 3, for example, when the MC4 starts operating by writing a command, the MC4 first writes *B.
*B is a response signal from MMPU3 with R set to LOW.
RJ (wait for it to go LOW. *When BR goes LOW, the address bus 14b and data bus 14 are released, so both the address and data are under the control of MC4. Therefore, MC4 indicates that the operation is being executed. *Starts operation at the same time as turning BGA LOW.When the operation is finished, MC4 *
Set BGA to HIGH and pass address and data bus management to MMPU3.

[ADRC4t5...Address counter] The ADRC415 in FIG. 2 specifies the address of the target memory, and is composed of a 16-bit counter.
~A1B, ie, has a variable range of 64 words. Since the memory 5 has a data width of 16 bits, the lowest address AO is not normally required as shown in FIG. 27, but the MC 4 is provided with a counter for the Ao.

The ADRC415 has a variable increment amount depending on the settings from the MMPU3, and its biggest feature is that it can set an increment amount of +3 and can control both 8 and 16 bit interface data widths.
The difference is that even if the increment amount is the same, the increment amount of ADRC 415 is different.

FIG. 21 shows a method of storing input data in the memory 5 when the interface bus width is 8 bits and the input data format is 24 bits vertically.

As shown in FIG. 23, as can be seen from FIG. 17, storing manual data in order in the memory 5 is the easiest form to process, including control during printing, so the increment amount of ADRC 415 is If set to +1, the change in address will be n, n+1 . . . if n is initially set. n+2.
n+3... yell. On the other hand, if the input data format is 24 bits vertically, the input data shown in FIG. 21 is stored in the memory 5 intermittently as shown in FIG. To do this, if the increment amount of the ADRC 415 is set to +3, the output address will be n, n+3°n+6, . . . , and the result will be the same as in FIG. 22. ADRC415
If we compare the case when the interface bus width is 8 bits and 16 bits when the increment amount of In the case of , the input data shown in Fig. 24 and the memory result shown in Fig. 25 are obtained.As can be seen from Fig. 25, the address output of ADRC415 is n,
n + 2, n + 4” - roar.

Increment amount other than the above description +2. +4...is...
This is to be able to cope with changes in the number of elements in the head used in the device. Note that +3 increments are effective only when using an 8-bit interface, and the configuration is such that when the bus width is 16 bits, the amount is automatically increased by +1 increments.

The above operation will be explained with reference to FIG.

PT810 is "1" when the increment amount is +3, otherwise it is "0", and PO312 is "1" when the increment amount is +3.
BW811 is a signal indicating the interface bus width, and is “1” when it is 8 bits.
”, is a signal that becomes “0” when it is 16 bits.802,
803 are binary counters. 801 is a ternary counter, but unlike a normal ternary counter, it reads 0 → 1 → 2 → 0.
Instead of changing as →1..., 0 → 3 → 2 → 1 → 0
→..., and a carry signal (not shown) is always supplied to a higher-order counter (not shown) when counting up other than O→3. As a result, if the initial value is 0, the lower 3-bit address changes from 0 → 3 → 6 → 9, etc.
If the initial value is 1, it becomes 1-4-7- A-...,
When the initial value is 2, the order becomes 2→5→8→B... Now, when the interface bus width is 8 bits and the amount of change is +3, PT=1. Since BW=1, AND gate 81
The output 816a of Ao8 becomes "1", and the address signal Ao8
14. A1815 has the output 801 of the ternary counter 801.
a, 801b are output. If the amount of change is +3 and the interface bus width is 16 bits, it is BW-0, and the AND gate 816 is prohibited.
6a becomes “O”, and from AND gate 813 becomes 802
a, 803a are output to outputs 814, 815. or,
PO312 is zero, but since PT=1, AND gate 808 is enabled and binary counter 803 is incremented. As a result, when the amount of change is +3 and the interface bus width is 16 bits, the mode is automatically set to +1 and the address signal Ao 814 does not change at all.

Next, when the amount of change is +1, since PT810=O, the AND-OR gate 81
3 selects 802a and 803a. Since the interface bus width is 8 bits and KBW811=1, the operation of the binary counters 802 and 803 is as follows.
02 is incremented and AND gate 806 is the carry signal of binary counter 803, so 802
When the binary counter 802 is incremented when a is "1", the binary counter 803 is also incremented at the same time. When BW811=O, that is, when the width is 16 bits, the AND gate 805 is prohibited, so the binary counter 802 does not change, but the AND gate 807
is enabled, so the binary counter 803 is incremented, resulting in n, n+2 . ...is obtained.

<BK414...Bank register> The color recording device has color memory divided into blocks. FIG. 8 is an explanatory diagram thereof, and each color is an address signal A,
7-A23. BR414 in Figure 2
consists of four trees of 7-bit registers, each of which can be set independently.

However, the Y bank must be set to #1, M to #2, C to #3, and BK to #4.

The reason for this is that the conversion order is fixed during the color conversion operation.

Although the C0MR413, which will be described later, has bits for selecting BR414, the register numbers pointed to by these bits correspond to the number of BR414. Therefore, MMP
U3 sets all BR414 at the time of initialization, and if you do not change it after that, even if you make a mistake in setting the lower address of A1-Ax13 when accessing memory using MC4, the address part of BR414 will not change. It has the advantage that the contents of the memory other than the one selected will never be destroyed. Furthermore, by having four BR414s, even if there is only one lower address register, there are apparently four address registers, which is extremely useful.

<C0MR413...Command register> C in Figure 2
0MR413 is a 16-pit register, and MMPU3 instructs to set the operation mode and start the operation by writing data to this C0MR413. Its contents include 4 bits for operating mode setting, 2 bits for interface bus width selection, 2 bits for BR414 selection, and ADRC41
5 bits for setting the increment amount, 4 bits for setting the last current to set the bit position of the target memory at the time of vertical/horizontal conversion, and 1 bit for starting the operation.

The instruction decoding circuit ID430 in FIG. 2 receives the information from the C0MR413 and starts control according to each operation mode.

<LC412...Length counter> Figure 2 LC41
2 is a 16-bit counter that sets the number of transfers, and is decremented by 1 when one transfer is completed.
When the contents of 2 become all 0, set the end bit 412a to 1"
to notify the ID 430 of the end of the operation.

Although the LC412 is a down counter in the above explanation, the internal circuit of the MC4 uses an up counter in order to simplify the circuit.

Therefore, in order to match the actual setting number and the number of transfers, MC
4 is ID4 when LC412 is selected by MMPU3
30 outputs a chip select signal 823 in FIG.

The chip select signal 823 is sent to the ninth chip by a circuit not shown.
When the inversion control signal 430a is set to "1", the invert circuit 416 inverts the human data 401 and outputs the data 41.
6b to the input terminal of the LC412 in FIG.

The LC412 takes in the output data 416b inverted by the chip select signal 823.
When PU3 writes the number of transfers 1, the output of LC412 is 'F
, FFE', the circuit for detecting the end of transfer is the 28th circuit.
As shown in the figure, an AND gate end state detection gate 821
All outputs of the LC412 are connected to the input. As a result, at the end of the transfer, all inputs are “1”, that is, ′
This is when FFFF' is detected. From this, when the above-mentioned 'FFFE' is set, when the LC412 counts up by the count-up signal LCP825, the output becomes 'FFFF', which means that the transfer ends with one increment for the set transfer number 1. .

After the power is turned on, the LC controller 412 is in a fail-safe state, so it is required that the transfer is completed, that is, all outputs are "1". However, even if the LC412 has a clear terminal, when the LC412 is cleared, all outputs become "0", so this embodiment does not indicate the transfer end state. Therefore, in this embodiment, the latch 820 shown in FIG. 28 is added. This makes it possible to enter the transfer completed state after power-on.

It is the output of the end state detection gate 821.
22 is connected, and one input of the OR gate 822 is connected to the output signal 820a of the latch 820. Since this output signal 820a becomes "1" with the clear signal 824, the output signal 822a of the OR gate 822 also becomes "1", so it is L
No matter what state the contents of C412 are, it indicates the end state. The latch 820 then outputs a signal 820 because the LC412 is in the selected state, that is, when the MMPU3 writes to the LC412, the counter set signal 823 becomes O.
a becomes “0”, and at the same time, 416b is added to LC412.
data is set.

As explained above, a fail-safe circuit can be easily completed by inserting one stage of latch, and the LC412 can be used as an up-counter without a clear terminal, so this example can be used as an IC.
It is clear that this greatly contributes to the reduction of the number of gates when

(Margin below) Each operation mode will be explained below.

[Write interface data to memory] (I
FR mode) This is the most basic operation of the MC4 of this embodiment.

The operation of writing the interface data 15 from the interface unit 6 of FIG. 1 into the memory at the address set in the ADRC 415 inside the MC 4 will be described.

FIG. 5 is a timing chart, and FIG. 6 is an operation flowchart, and the explanation will be based on these.

In both FIG. 5 and FIG. 6, explanation of the portion of returning the MMPU 3 to the stopped state or to the operating state is omitted.

In FIG. 6, in step S61, DRQlol, which is an interrupt signal from the interface unit, goes high.
After detecting that the address bus 14b and data bus 14 are under the control of the MC 4, the contents of the BSEL 417 and ADRC 415 in FIG. 2, that is, the target memory address, are output in step S62. In step S63, the *IFR 106 is set to LOW in order to subsequently output the data stored in the interface unit 6 to the data bus 14 in FIG. In step S64, when the operation mode is IFR, the process advances to step S65.
The case when the mode is not IFR, that is, the DD mode will be described later. In step S65, the RW105 signal indicating the read/write status is set to LOW, and the *AS104 indicating the address strobe is also set to LOW. In step S66, the process branches depending on whether the bit width of the interface data 15 is 8 bits or 16 bits.

Now, assuming that the width is 8 bits, the process advances to step S67.

In step S7, it is determined whether the valid data on the data bus 14 is the upper 8 bits (Do to Dz5) or the lower 8 bits (Do to Dz5).
~D7) j+UDs102 and *LDS103
Output. Based on these two signals, the memory 5 determines the data to be fetched. At this time, since the ADRC415 only has addresses 1 (A1) to 15 (A15) L/, a flip-flop for address 0 (AO) (not shown, address *UDS, depending on the value of (see counter explanation)
*Determine LDS. Step S68 is the final step of the write cycle to the memory, and *As104, *U
DS102. *RW105. *All IFR106) (
At the same time as setting the address bus 14b to IGH, the address bus 14b and data bus 14 are transferred to
4b, the data bus 14 is disconnected and the process ends.

Next, we will explain when the interface data bus width is 16 bits, but before that, we will use Figure 4 to explain the case where the interface data bus width is 8 bits/8 bits.
The switching operation for 16-bit width will be explained. When the interface data 15 is 16 bits wide, the data on the data bus 14 is the same as the interface data 15, but when it is 8 bits wide, the data of the interface data 15 is Do-D7 (lower 8 bits) of data bus 4.
Odd addresses (Ao = 1)
In order to write to the memory of the data bus 14, it is necessary to give the same information to the upper 8 bits of the data bus 14 as to the lower 8 bits.
The lower 8 bits of are always sent to MC4 via buffer 14e.
It is supplied to the lower 8 bits of the internal data bus IDo-15 (indicated by 401). However, during operation in this mode, I Do-15 is not used inside the MC4.

Now, when the data bus width is 8 bits, the data bus 14
The upper eight bits of the data bus 14 are connected to the B input of the data selector 108, and the lower eight bits of the data bus 14 are connected to the A input. BW811 is 1 when the data bus width is 8 bits.
”, the output Y of the data selector 108 has A
The input data appears. Since the buffer 14C has a three-state control terminal, the buffer 14C is enabled when BW811 is "1", so the same information as the lower 8 bits appears in the upper 8 bits of the data bus 14. Similarly, when the data bus width is 16 bits, BW811
Since the buffer 14C is 0", the buffer 14C is disabled and has no effect on the upper 8 bits of the data bus 14. Also, the upper 8 bits of IDo-x5 are the upper 8 bits of the data bus 14. The same data is output.

By having this function, which is an embodiment of the present invention, when the memory data bus width is 16 bits, the output interface data 15 of the interface unit 6 in FIG. 1 is composed of 8-bit wide data lines. Also, 16
Even if the data width is bit width, the MMPU 3 only sets the data width of the interface to the MC 4 once and is not concerned with the rest, and the interface data 15 is written to the memory 5 in an orderly manner, so the data management method is becomes very easy.

Next, we will explain the 16-bit data width in IFR mode in the sixth section.
In the figure, steps 361 to 66 are the same as in the case of the 8-bit data width. The difference is that step S66 branches to step S69, and in step S69, since the data width is 16 pits, *ID5102. *This is to set both LDS103 to LOW. After step S69, the process proceeds to step 36B, thereby completing the operation. FIG. 5 shows the above explanation in terms of timing.

[Impair reading of interface data] (DD mode) This mode is a function that merely reads the data in the interface unit 6, but does not write it anywhere in the memory. Referring to the flowchart of FIG. 6, steps S61 to S64 are the same as in the IFR mode, and the process branches from step S64 to step S68.

This means that the signals *AS, *UDS, and *LDS are necessary for reading data into the memory 5.

This is an operation mode in which no RW is output, that is, no writing is performed.

This function is very effective in the following cases.

This is because when the host CPU sends print data beyond the printable range of the color recording device 2 (see Figure 1), the color recording device 2 must discard the excess data, but this operation is handled by the software MMPU 3. It takes a very long time to process with this control.

At this time, if this function is used, the MMPU 3 only needs to set the command and the number of transfers to the MC 4. Therefore, the overhead between reading software interface data and other jobs is significantly reduced.

[Color conversion] (CCD mode) Y (yellow),
BK from three color data of M (magenta) and C (cyan)
The CC mode generates (black) data. Second
7 and 8, but before that, the color conversion generation formula used in this example will be described as follows: BK = Y - M - C Y' = Y - BK M' = M-BK C'=C-BK (Y', M', C' are Y, M, C data after color conversion).

FIG. 8 shows the structure of storage addresses for each color data in this embodiment. Address signals A17 to A23 separate Y, M, C, and BK, and address signals A1 to Ax
(Ao does not exist because the width is 16 data), each word data is accessed. A point to be noted in this configuration is that the starting addresses of each color data (only the range indicated by Ax-Aza) must be the same.

The commands and data sent from MMPU3 to MC4 in FIG. 1 include start address data to ADRC 415 in FIG. 2, number of words transferred to LC 412, B
Bank #1 (Y data memory) to R414, bank #
2 (M data memory), bank #3 (C data memory)
, Bank #4 (BK data memory) data settings,
Finally, there is a color conversion command to C0MR413.

After receiving the color conversion command, the MC4 transfers the address bus 14b,
When the data bus 14 comes under the control of the MC 4, color conversion starts. FIG. 7 is a timing chart showing the execution state, and Al-A23 is an address signal, especially AL T
-A23 is the upper 7 bits of the bank address and A17-
#n in A23 is the bank number. This indicates that data corresponding to bank #n set in the BR414 is output, and n of Ax-Ate is ADR, C4
Indicates data set to 15, and data Do −1
I or 0 in 5 indicates the direction of data, ■ indicates the transfer direction from the memory 5 to the MC4, and 0 indicates the transfer direction from the MC4 to the memory 5. *AS, *UDS, *LDS, and RW are all signals output by the MC 4, and the memory 5 uses these signals to control data input or output.

The color conversion procedure for one word will be explained step by step with reference to FIG. In step S71, the address outputs bank #1 (Y data memory 501 in FIG. 8 is selected),
The Y data is taken into the DR410 in FIG. Step S7
2, output bank #2 (M data memory 5 in Figure 8).
02), and the M data is taken into the DR411 in FIG. 2. In step 373, the AND circuit 41 is
8, DR410 and DR411 are ANDed, and the ANDed data is taken into DR411. In step S74, bank #3 is taken into the output (C data memory 503 in FIG. 8) Lz, DR410. Step S7
5, the operation is exactly the same as step S73, but as a result, Y*M*C, that is, BK data remains in the DR 411. In step S76, bank #4 (BK data 504 in FIG. 8) is output and written into the memory.

In step S77, new Y, M.

In preparation for generating C data, BK data is inverted and rewritten to the DR 411.

This means that the ID430 converts the inversion signal 430a in FIG.
By supplying the data to the INV 416, the data on the internal data bus 401 is inverted and becomes the input to the DR 411. This is explained in FIG. 9. In the case of non-inversion, the inversion signal 430a is "0", so the internal data 401 is supplied to the DR 411 without being inverted, and in the case of inversion, the inversion signal 430a is "1". ”, the internal data 401 is inverted and supplied to the DR 411. With this operation, an inverted signal can be easily obtained. In step 578, the Y data is loaded into the DR 410.

In step S79, the AND signal of DR410 and DR411, that is, new Y data, is written to the Y data memory 501.In step S80, M data is taken into DR410.In step S81, DR410 and DR411
In step S82, the new M data is written to the M data memory 502, the C data is written to the DR410.
Incorporate into. In step S83, DR410 and DR4
11 AND signal, ie, new C data, is written into the C data memory 503. At this step, the color change of one word is completed, so add 1 to ADRC415, and then add 1 to LC41.
Subtract 2 by 1. As a result, if the content of LC412 is not zero, the next word conversion is executed as shown in FIG. 7, and if it is zero, the process ends.

As described above, according to this embodiment, the color conversion of one word (two bytes) is performed without interruption to the memory 5, so it can be seen that it can be executed much faster than conversion by software.

[Vertical/horizontal conversion] (MV mode) This mode is used when the data format from the host CPUI is a raster image format, and is shown in Figure 10 (a).
) to (C) are diagrams comparing input data from the host CPUI and the contents of the memory after conversion. The input data (output data from the host CPU 1) when the interface bus width is 8 bits is shown in FIG. 10(a), and the contents of the memory 5 after execution of this mode are shown in FIG. 10(b).

It is shown in (C). In both FIGS. 10(b) and 10(C), the shaded areas indicate that the contents have not changed at all from before the execution of this mode. FIG. 10(b) is the result of executing MSB first conversion, and FIG. 10(C) is the result of executing LSB first conversion, and the differences between the two will be described later.

Here, the HV mode will be explained with reference to FIGS. 2, 11, and 12 on the premise of MSB (D7) optical conversion. Note that the part for importing the interface data 15 is omitted, and it is assumed that the data in FIG. 10(a) is stored in the DR 410.

In Figure 11, BCNR421 is an octal binary counter,
PS420 (7) PSMX is Y with 8 → 1 multiplexer
is a positive logic output, BCSL of BC419 is a 4→16 data selector, and BCAI to BCA32 are AND gates.

Explaining according to Fig. 12, the address at the start of operation is m
, LDDl (indicating MSB first conversion), the bit designation signal 430b of the target memory in FIG. 11 is 430b-0==Q
So 430b z=430b 2-430b-3-0
, this 430b means that the data in the DR 410 specifies Dl in the memory in the example of FIG. 10(b).

In step 5121, the data at address m is DR
411.

In step 5122, the first bit obtained by parallel-to-serial conversion of the output of DR411 appears at 420a in FIG.
410 by replacing the output of 0 with Dl of 410a in FIG.
If the data other than D1 of a is written to the memory at address m without changing at all, the BCNR421 will be all “0”.
”, and since LD=1, PSMX(7) input A,
B and C are all “1”, so PSMX output Y
Dl of the output 411a of the DR 411 is output to 420a. On the other hand, the output of BCSL is 0 when the input is A=1, so only BC3LI is "0" and everything else is "1", so the output 410a of DR140 is B
CAI, BCA5°BCA9. -, since the BCA31 is enabled, the internal data bus 401 has 4 bits except Dl.
The same data as 10a is output. BCA3. BCA4
Since BCAL1=O, BCA3 is disabled and BCA4 is enabled, so the signal 420a, that is, the MSB of 411a, is output to the internal data bus 401. This results in the same result as the address m in FIG. 10(b).

At the end of this step BCNR421 and ADRC41
Prepare for the next step by adding 1 to 5.

As a result, the address Ax -Ax 8 is m+1, B
Output of CNR421 421a=1,421b-421c
=O5 or inputs A and B of PSMx.

C is A=0. B=C=1.

In step 123, data at the address indicated by Al-Ala is taken into the DR 411.

Step 124 is the same as step 122, except that the content of the output Y420a of PSMX is selected by inputs A, B, and C of PSMX (Do is selected in step 124).

The above is done in odd number steps (121, 123°125-・
), even steps (122, 124°126...)
The same operation as LC4 is repeated in step 5136.
Since the operation of decrementing 21 by 1 is added and the conversion is completed at step 136, the operation of MC4 itself is completed and MNPU
The management of the address bus 14b and data bus 14 is transferred to the address bus 14b and the data bus 14.

The above explanation is based on the data stored in DR411.
This is a mode in which conversion is performed with B (Dl) at the beginning, but a feature of this embodiment is that it is provided with a mode in which conversion is performed with LSB (00) at the beginning.

To implement this method, when the MMPU3 sends a command to the MC4, a switching command for MSB/LSB is provided (or by an external terminal of the MC4), so that the LD signal shown in FIG. By setting it to “0” in the previous case, it becomes the selection input terminal A of PSMX.

B and C become D by inverting and non-inverting the output of BCNR421.
It is determined whether the selections are made in order starting from 7 or whether it is Do.

By providing the tree function, there are two types of raster formats from host CPU 1.
This has the advantage of being easily selectable as a processing method within I.

Also, in the above description, the interface path width was 8 bits, but a feature of this embodiment is that a 16-bit bus width can also be selected (see IFR mode). Taking Figure 11 as an example, BC
This is realized by making the NR421 a 4-bit counter and changing the PSMX from the 8→1 multiplexer in FIG. 11 to the 16→1 multiplexer.

As described above, according to this embodiment, vertical and horizontal conversion of 1 byte, 8 bits can be performed in a short time of 16 steps. now,
If one memory cycle is 250ns, then 250nsX
It will end in 16=4ns.

[Fixed data writing] (C0% CDHV-!--de) This example is simple and operates as a MAC, but the D
It has functions that MAC does not have.

These are the fixed data writing modes, ie, CD mode and CDHV mode.

In this mode, when data is written to DR411 in MC4, data in DR411 is continuously transferred to memory 5 for the number of transfers.
This is the operation of writing to.

The CD mode has exactly the same operation as the IFR mode, and the CDHV mode has the same operation as the HV mode except for the following points.

The difference is that the target conversion data is data written to DR411 in CD and CDHV modes, and interface data in IFR and HV modes.
In the HV mode, the number of transfers set in the LC 412 is continuously executed. This is explained in Figure 13 (
a).

(b) and Fig. 13 (a) are explanatory diagrams of IFR and HV modes, where DRQ is an interrupt signal from the interface unit 6, and when MC4 detects DRQ, it becomes a management light for the address data bus, and after completing the specified processing. Pass control of the bus to MMPU3. One byte (or one word) is processed in one processing at this time.

FIG. 13(b) is an explanatory diagram of the CD, CDHV-1--. When the MMPU3 writes a command to the MC4, the M
The C4 continuously processes the amount set in the LC412, so if the number of transfers is large, the time until the MMPU3 becomes operational becomes longer.

14(a) and 14(b) show the contents of the memory 5 after executing the CD and CDVH modes, respectively.
(b) It is very effective when used to clear the memory as shown in the figure. To write a staggered pattern as shown in Figure 15 to the memory 5, 1. Set the nearest start address to 1. 2. Set the increment amount of the near address counter to +2. 3. Set the number of transfers N to the length counter. 4. Set the DR411. °
Set 1010101010101010° 5: Send CD command: (MC4 executes CD mode) 6: Set start address to n+1 7: Set address counter increment to +2 8: Set transfer number N to length counter 9 :DR411 to X' 010101
Set 0101010101 10: Send CD command (Execute CD mode) This has the advantage that a staggered pattern can be created at high speed simply by performing the following control.

[Data inversion] (■FRx, uvx-v--de)
Both modes perform the same operation as the IFR, 1 (V mode), but this mode differs from the IFR, HV mode in that the interface data 15 is inverted and used.

To explain the IFRI mode in Figures 9 and 29, I
In the FRI mode, the signal 430a in FIG. 9 is set to "1".
' and import the interface data 15 into the DR441. Since the signal 430a is "1", the inverted data of the internal data bus 401 is stored in the DR 411. Next, when *IFR in FIG. 29 is set to "1", the data bus 401 becomes a floating state, so the MC4 outputs the contents of DR411 to the external data bus 14, and further sends control signals *UDS, *LDS, *AS,R
Output W and exit.

In the HVI mode, the only difference is that 4038 in Figure 9 is set to "1" and the inverted interface data 15 is loaded into the DR411, as in the IFRI mode, and everything else is the same as the HV mode. be.

The advantage of the wood mode is effective when converting RGB data to YMC data. This is shown in Figures 19 and 30.
To explain using figures, Fig. 30 (A) is different from Fig. 19 (
The data format of A) and FIG. 30 (B) explain an example of the data format of FIG. 19 (C). Since the data format of FIG. 1M is bank #1 in bank #1 of
2, C should be stored in bank #3, this is the 30th
As explained in Figure (B), when setting the IFR mode, select the link number #1. #2゜It is sufficient to perform in the order of #3. On the other hand, the data format in Fig. 19 (A) is RGB.
Since it is a format, it is necessary to convert it to MMC. To do this, we perform the transformation represented by the formula is R, so bank #
3, next is M, so select bank #2, and last is B, so select bank #1. MMPU3 can execute the software related to color conversion by commands, addresses, and commands for MC4. It is very efficient because it only requires setting the number of transfers.

After this, the above-mentioned CC mode is used to convert YMC to YMCB.

(Auto refresh function) If the printable area of this color recording device is 8 inches and the horizontal dot resolution is 200 dpi (dots/inch), the memory capacity required for one line is 8 (inches) x 2.
00 (dpi) x 24 (element/head) x 4
(Number of heads) - 153,600 bits, and if this is expressed in number of bytes, it becomes 153,600÷8=19.2KB. Of course, static RAM would be used for this amount of capacity, but in another application, the printable area is 15 inches,
Assuming a device with a dot resolution of 400 dpi and 128 elements/head, the memory capacity will be 384 KB, so a dynamic RAM may be used as the memory. Dynamic RAM has the disadvantage that memory contents change unless it is refreshed periodically. The refresh circuit creates a refresh signal under the control of the MMPU 3, or detects free time inside the memory 5 between accesses from the MMPtJ3 and creates a refresh signal. However, in this embodiment, especially in color conversion, the color conversion is executed within the cycle time limit of the memory 5, and since it is impossible for the MMPU 3 to interrupt the execution while it is being executed, there is a possibility that refreshing will not be possible. I'm coming.

To compensate for this drawback, the MC4 is provided with an ARI signal (not shown) as an external terminal, and when the ARI signal is "1", the CC
Auto-refresh is performed only on -T-, CD, and CDHV-r-- modes. The reason why auto-refresh is not executed in modes other than the above is that in those modes, the time during which the MC4 manages the address bus 14b and data bus 14 in FIG. 13(a) is less than 1 μs; This is because control of the address bus 14b and data bus 14 returns to -HMMPU3 every time execution is performed.

On the other hand, in CC, CD, and CDHV modes, the 13th
As shown in Figure (b), for a long time the address bus 14b
This is because the MC 4' manages the data bus 14. This will be explained using FIG. 7 and FIG. 31, taking the CC mode as an example.

FIG. 7 shows an example when auto-refresh is not executed, and step n in the CC mode is a repetition of steps 71 to 83.

On the other hand, when auto-refresh is executed, one cycle of dummy steps is inserted between step S83 and the next step S71, as explained in FIG. 31, and at this time a refresh pulse *RF is output. At this time *AS, *LD
S.

R3 is all "B". A1-A23 in FIG.
This is because it does not have an address counter for refreshing. Therefore, when the memory 5 receives II'tF, it performs refresh using its own address counter.

(LC latch, ADRC latch) MM when storing data in the MMC data format shown in Figure 19 (C) in the memory 5 using IFR mode
The outline of the commands etc. that the PU3 sends to the MC4 has already been described in Figure 30 (B), but to explain this in more detail, there are three processes: address counter setting, length counter setting, and command setting. The IFR mode is executed by repeating this three times, but as explained in Figure 19 (C), the length counters are data of the same length for Y, M, and C, and the contents of the address counters are also color converted. Because data must be stored from the same address for processing reasons, it is necessary to set the same data. Therefore, LC412, ADRC41
If a latch is provided in the data input section of 5, ADRC415,
Settings for LC412 only need to be done once, so MMPU
Processing on the third side is greatly simplified. This is explained in FIGS. 32 and 33. LC412, ADRC41
5 only have different functions and are the same in terms of data settings, so only the LC 412 section will be explained.

FIG. 33(A) is an address assignment table for registers and counters before a latch is provided, and for convenience of explanation, $1 is left blank. When setting data to the LC 412, the MMPU 3 writes to address XXXX2, and the data at that time is stored in the LC 412.

FIG. 33(B) is an address assignment table when a latch is provided, and although it is not changed from FIG. 33(A), the circuit is different. That is, a latch 831 is provided in front of the human power section of LC412 in FIG.
Take in b. When MMPU3 writes data to address xxxx2 in FIG. 33(B) in order to set data in LC412, the clock signal 833 of latch 831 in FIG. 32 becomes "1" and latch 831 writes data 41.
6b is taken in, followed by MMPU3 C0MR41
When data is written to 3, the signal 834 becomes '0''' and becomes L.
C412 takes in latch 831 and data, and by this circuit, 1 is input before snap 5311 in FIG. 30(B).
It is only necessary to set data to the ADRC 415 and LC 412 once, and steps 3312 and 5313 are not necessary.

It is obvious that the load on the MMPU 3 can be further reduced by implementing the circuit described above.

However, when the human data format is raster image data, MMC format, 1 color data is 10
When it is 0 byte, as explained in FIG. 34, from receiving the manual data to printing, in step 5341, the ADRC 415, that is, the start address setting is O in this example, and the LC 412 is set to 100 bytes for 1 color data. Since it is a byte, set it to 100.

In step 5342, the vertical/horizontal conversion HV mode is repeated 72 times. The color specification format for this is Y.

2 because it is M, C and the number of head elements is 24.
Since data is received 4 times, the number of vertical and horizontal conversions is 3x24.
=72.

In step 5343, the address and the value of LC412 are reset to execute the color conversion CC mode. ADRC
415 can be set to 0, but for LC412, the manual data should be set to 100.
As explained in Figures 10(a) and (b), the byte is converted horizontally and vertically, so it is stored in the memory multiplied by eight in the horizontal direction, so 100X8=800,800 is stored in the LC412.
Set to .

In step 5344, the CC mode execution step 53
In step 45, the process for one printing is completed after printing is executed, and the process proceeds to step 53.
41, but at step 5341, ADRC4
15. A specified value must be set for LC4t2.

A circuit devised to improve this point is shown in Figure 35.
As a result, after the first printing is completed in FIG. 34, instead of returning to step 5341, the process returns to step 5342, as shown by the dotted line. Due to this, MMPU
The software in No. 3 is further simplified. The method will be explained below.

Figure 33 (C) is an address allocation table when the improved plan is implemented. The difference from Figures 33 (A) and (B) is that $1 is the command register, $4 is the length latch, and $5 is the address latch. This is the point I made.

FIG. 35 shows an example of a circuit, in which the latch 831 in FIG. 32 is changed to a latch with a tri-state buffer, and the circuit changes from FIG. 32 to FIG. 35 by adding a tri-state buffer 830.

When the MMPU 3 selects the length counter $2 in FIG. 33(C), the signal 832 becomes "0" and the rebuffer 83
0 is enabled and the buffer part of the latch 831 is disabled, so the internal path 416B appears at the input part of the LC412, and at the same time the signal 823 becomes 0'', so the output 835a of the OR gate 835 also becomes 0. ,
The same data as 416b is taken into LC412.

When MMPU3 selects length latch of $4, signal 8
33 becomes "1", and the latch 831 takes in the data of 416b. The data captured in this latch 831 is
In order to transfer to C412, MMP'LJ3 only needs to select the command register of $1. At this time, signal 8
32 is "1", the buffer 830 is disabled, and the output of the latch 831 is enabled, so 83
The contents of latch 831 appear in 0a, and as a result, LC4
FIG. 36 shows a relationship of 0 or more in which the same data as the contents of the latch 831 is taken into the latch 831.

The operation of FIG. 34 by this circuit is as follows: In step 5341, the start address is set in the $5 address latch, and the number of transfers, 100, is set in the $4 length latch.

In step 5342, the operation of setting the HV command in the $1 command register is repeated 72 times.

In step 5343, the start address is set in the address counter of $3, and the number of transfers, 800, is set in the length counter of $2.

In step 5344, CC is written to the command register of $0.
Set the mode and execute.

In step 5345, printing is executed, and after completion, step 5
Return to 342.

In the above explanation, there are two C0MRs 413, but in reality there is only one register, and it is designed to operate differently depending on the address.

As mentioned above, the present invention has the effect of greatly simplifying the MPU software by applying it to a color recording device in particular, and also has a large capacity because it executes interface data import, color conversion, vertical/horizontal conversion, etc. at ultra-high speed. A color recording device with high throughput can be realized even with data of

(Blank below) [Effects of the Invention] According to the present invention, when memory is occupied for a long time by providing a complex function in memory control using the direct memory access method, if the memory is volatile, it can be refreshed. By outputting pulses, it is possible to provide a memory control circuit that does not destroy memory contents. In other words, the present invention makes it possible to provide complex functions to memory control using the direct memory access method.

(Margin below)

[Brief explanation of drawings]

Figure 1 is a block diagram of the color recording device, Figure 2 is a block diagram of the memory control circuit, Figure 3 is a timing chart of the use of the memory control circuit data bus and address bus, and Figure 4 is 8-bit width/16-bit width. Switching circuit diagram, Figure 5 is a timing chart of IFR mode, Figure 6 is a flowchart of IFR mode, Figure 7 is a timing chart of CCD mode, Figure 8 is an addressing diagram of the memory control circuit, Figure 9 is inverter logic. Circuit diagram, Figures 10 (a) to (c) are HV mode explanatory diagrams, Figure 11 is MV conversion circuit diagram, Figure 12 is HV mode timing chart, 3i13
Figure (a) is an explanatory diagram of IFR and HV mode, Figure 13 (b)
is an explanatory diagram of CD, CDHV mode F, Fig. 14 (a) is a memory state diagram after executing CD mode, Fig. 14 (b) is an execution state diagram after executing CDVH mode, Fig. 15 is a staggered pattern formation state Figure 16 is a comparison diagram of input data and output results in Lester format, Figure 17 is a comparison diagram of human data and output results in vertical 8-bit image format, and Figure 18 is a comparison diagram of vertical 24-bit image format. A comparison diagram of input data and output results, Figures 19 (A) to (D) are color specification format side ports, Figure 20 is a diagram explaining color conversion, Figure 21 is a diagram of 8-bit width manual data, Figure 22 is vertical 8
Fig. 23 is a storage state diagram when formatting 24 bits vertically with 8-bit width input; Fig. 24 is a diagram of input data with a 16-bit width; Fig. 25 shows an 8-bit width input data diagram.
Storage state diagram for vertical 24-bit format with bit width input, Figure 26 is a partial circuit diagram of the address counter, Figure 27 is an address designation diagram of the memory control circuit, Figure 28 is a length counter circuit diagram, and Figure 29 is a diagram of the address counter. Timing chart of IFRI mode, Figure 30 (A) is a flowchart of IFRI mode, Figure 30 (CB) is a flowchart of IFR mode, Figure 31 is a timing chart of auto-refresh, Figure 32 is a latch circuit diagram of length counter, Figures 33 (A) to (C) are explanatory diagrams of commands to the memory control circuit, Figure 34 is a flowchart of the mask MPU, Figure 35 is a control circuit diagram of the length counter and latch, and Figure 36 is the length counter and latch. FIG. 2 is an explanatory diagram of a control circuit. In the figure, 1... host CPυ, 2... color recording device, 3... master MPU, 4-... memory control circuit, 5
...Memory, 6...Interface unit, 7
...Sub MPU, 8...Print head, 9...Paper feed motor, 10...Carriage motor, 410°41
1... Data 23 storage register, 412... Length counter, 413... Command register, 414...
・Bank register, 415...address counter, 4
16... Inverter logic, 417... Bank selector, 418... AND logic, 419... Bit change, 420... Parallel to serial conversion circuit, 421...
・Bit counter, 430... Instruction decoder, 440... Micro sequencer, 450...
・It is a bus arbiter. Patent applicant: Canon Corporation Figure 5 Figure 9 Figure 13 (G) ai Figure 13 (b) 1! +7rIA Printed Koto Ito Zhanka No. 1 Old District Printed Soil Result Figure 19 (A) Side 19 (C) Figure 19 (D) Figure 20 Figure 21 Prisoner Figure 22 23rd Cause 24rIA Figure 25 31ffl Haku 32nd Ward 33rd Ward (A) 33rdffl (B) 33rd rlA (C) 34th rIA

Claims (3)

[Claims] (1) A memory control circuit that controls a memory using a direct memory access method, characterized in that the memory is equipped with an output means for outputting a refresh pulse when volatile memory is monopolized by continuous control exceeding a predetermined length of time. control circuit. (2) The memory control circuit according to claim 1, wherein data is controlled in units of 16-bit width. (3) The memory control circuit according to claim 1, wherein data is controlled in units of 8-bit width.