JPS62217767A - Memory control circuit - Google Patents

Abstract

PURPOSE:To obtain a memory control circuit storing data in a memory according to a data array matching to output elements by providing a means swapping crosswise a data array and storing input data according to the data array matching to a string made of output elements. CONSTITUTION:Based on a synchronizing signal made by a microsequencer 440, the memory control circuit 4 decodes contents in a command register 413 by an instruction decoder 430, controls a memory through a bus arbiter 450 or acquires the synchronization of a host CPU with a master MPU. On the other hand the circuit 4 converts data through the use of data storage registers 410 and 411, an inverter logic 416, an AND logic 418, a parallel/serial converter circuit 420, a bit change 419, a bit counter 421. An address counter 415 and a length counter 412 are used when the memory control circuit 4 repeatedly processes data with the same length at the same address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control circuit that controls a memory. In particular, it relates to a memory control circuit of an image processing device.

[Prior Art] In image processing devices such as color recording devices controlled by microcomputers (hereinafter abbreviated as MPU), the demand for high-definition output has increased significantly, and with this, the print heads of color recording devices have also improved. It has become high resolution. On the other hand, the amount of information per screen has increased significantly. Therefore, in order to increase the recording speed, the host CPU
The processing time required to capture data from the computer and generate BK (black) data from Y (yellow), 1M (magenta), and C (cyan) data is becoming longer and longer. In particular, it is desired to be able to print rask information at high speed with a so-called serial printer, which has a plurality of printing elements arranged vertically in a line and performs printing while operating horizontally with respect to the medium.

To do this, it is necessary to temporarily store the sent rask information in a memory, and after receiving the required amount of rask information, perform data conversion, that is, vertical/horizontal conversion, in accordance with the head fabrication under the control of software or the like. However, when receiving and converting data using software, the processing time is short when the number of elements in the head is small, so there is no problem, but the number of elements increases, and especially in the case of color data, it is usually
(red), G (green), B (blue) and monochrome data.
Since the amount of data is doubled, the data processing time becomes extremely long, and since the ink colors of the print head are Y, M, C, and I3, there is no need to convert RGB data to YMC data, which increases the processing time. It had the disadvantage of being long.

[Problems to be Solved by the Invention] The present invention has been made in view of the above drawbacks, and includes a function of converting horizontal data to vertical data, a function of converting input color data to corresponding color data, A format conversion function that adapts vertical n-byte image data to the head structure, a memory clear function, a function to discard input data that exceeds the printable range, and a function for when the target memory system is composed of dynamic RAM. The present invention provides a memory control circuit for an image processing device that executes an auto-refresh function at high speed.

c. Means for Solving Problem] As a means for solving this problem, the color recording device 2 shown in FIG. 1 is connected to the host CPU by an interface cable 16, and the interface data width is 8 bits. Or it is composed of 16 bits. The color recording device 2 includes a master MPU 3, a carriage motor 10, a paper feed motor 9, a sub MPU 7, a print head 8, a memory 5, an interface unit 6,
and a memory control circuit 4.

The memory control circuit 4 shown in FIG.
15, bank register 414, and bank selector 41
7, length counter 412, data storage registers 410, 411, inverter logic 416, AND logic 418, command register 413, instruction decoder 430, and bus arbiter 450.
, a micro sequencer 440, and a parallel-to-serial conversion circuit 420
, a bit change 419, and a bit counter 421.

Furthermore, an address counter 415 and a length counter 41
2, a latch is placed in the front stage.

[Operation] In this configuration, image data having a data width of 8 bits or 16 bits transmitted from the host CPU to the interface cable 16 to the interface unit 6 is stored in the memory 5 under the control of the memory control circuit 4. The color recording device 2 is controlled by the master MPU 3 and has a function of converting horizontal data to vertical data, a function of converting input color data to corresponding color data, and making the image data of vertical n bytes correspond to the structure of the head. The memory control circuit 4 has a format conversion function, a memory clear function, a function to discard input data exceeding the printable range, and an auto refresh function when the target memory system is configured with dynamic RAM. Before and after storage, the input data is converted into print data and output to the print head 8. On the other hand, sub M
The carriage motor 10 and paper feed motor 9 are controlled by the PU 7.

When the memory control circuit 4 is activated, the mask MPU 3 sets the start address in the address counter 415, sets the address for determining the area in the bank register 414, sets the data length to be processed in the length counter 412, and sets the data length in the command register 413. Memory control times wI
Set the command data that specifies the assistant production according to 4.

The memory control circuit 4 decodes the contents of the command register 413 with an instruction decoder 430 based on the synchronization signal from the microsequencer 440, and controls the memory 5 through the bus arbiter 450 or controls the host C
The data storage register 41o is synchronized with the PUI and the master MPU3.

Data storage register 411. inverter logic 416
, ANDLogic 418. Parallel to serial conversion circuit 420, bit change 419. Using the bit counter 421,
Perform data conversion.

Furthermore, an address counter 415 and a length counter 41
The latch in the preceding stage with 2 is used when the memory control circuit 4 repeatedly processes the same data length from the same address.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a color recording device to which an embodiment of the present invention is applied. The color recording device is connected to a post CPU by an interface cable 16, and the interface data width is configured to be 8 bits or 16 bits. ing. The color recording device 2 is a mask M that controls the whole
PU3 (hereinafter referred to as MMPU3) is a sub-MPU7 (hereinafter referred to as SM
PU 7) and is tightly connected by a wire 12. Furthermore, MMP
U3 is print head 8. Memory 5. It controls the interface unit 6 and memory control circuit 4 (hereinafter referred to as MC4). In this embodiment, the print head 8 has 24 dot elements per head.

FIG. 2 is a block diagram of MC4, which is the gist of this embodiment.
Briefly, an address counter 415 (hereinafter referred to as ADRC 415) determines the data transfer destination, a puncture register 414 (hereinafter referred to as BR 414) for specifying a color memory in the memory configuration shown in FIG. 8, and selects the BR 414. A bank selector 417 (hereinafter referred to as BSEL417), a length counter 412 (hereinafter referred to as LC412) that specifies the number of data transfers, and a data storage register 4 for internal work.
10 (hereinafter referred to as DR410), 411 (hereinafter referred to as DR411)
and inverter logic 416 for inverting the data.
(hereinafter referred to as INV416), the DR410 and DR411
AND logic 418 (hereinafter referred to as AN
D418), a command register 413 (hereinafter referred to as C0MR413) for setting the operation mode, an instruction decoder 430 (hereinafter referred to as ID430) for analyzing commands, and a bus arbiter 45o (hereinafter referred to as BA450) for synchronizing control signals with external devices. ) and a microsequencer 44 that generates the internal timing necessary for execution processing.
0 (hereinafter referred to as Ms440), a parallel-to-serial conversion circuit 420 (hereinafter referred to as PS420) that performs horizontal-vertical conversion, a bit change 419 (hereinafter referred to as BC419), a bit counter 421 (hereinafter referred to as BCNR421), and the like.

Furthermore, since the MMPU 3 is a 16-bit MPU with 16 bits of data and 23 bits of address, the memory 5 also has a data width of 16 bits. However, the output data 15 of the interface unit 6 is
Depending on the PUI, both 8 bits and 16 bits can be selected by setting the MC4.

Before giving a detailed explanation of the inside of the MCJ, the external specifications of the M and C4 and the general specifications of the color recording device 2 will be explained.

Specifications of the color recording device 2> 1. Head configuration: 1 x 24 dots/head, Y,
4 heads for M, C, and B 2, manual data format...Rusk image format...vertical 8-bit image format...vertical 24-bit image format 3, color specification format...RGB... RGBBK...MMC...YMCBK The above 2 and 3 will be explained using Figures 16 to 19, but to simplify the explanation, input data will be limited to results for one color in 8-bit width. There is.

FIG. 16 is a diagram comparing the input data and the output result in the raster image format, in which vertical 8-bit input data is regarded as serial data in bytes and output. Control during this format will be explained in detail in the section [Vertical/horizontal conversion (HV mode)].

FIG. 17 is a diagram showing the relationship between input data and output results in a vertical 8-bit image format, where manual data is printed only on dots 1 to 8 of the head. This means that dots 1 to 8 are not always printed each time one manual data is input, but usually three blocks of manual data are received and then printed. That is, the first input data block corresponds to dots 1 to 8, the second input data block corresponds to dots 9 to 16, and the third input data block corresponds to dots 1 to 1.
7 to 24 are printed.

FIG. 18 shows the relationship between input data and output results in a vertical 24-bit image format, where human data is interpreted as a byte serial format, and every 3 bytes corresponds to one vertical line of the output results.

Figures 19 (A) to (D) are examples of color specification formats, and Figure 19 (A) is an RGB format, where color data is provided every N bytes (corresponding to the input data in Figures 16 to 18). is changed. Similarly, Fig. 19 (B) shows RGBBK
, FIG. 19(C) is MMC, FIG. 19(D) is MMCB
It is in K format. The ink color of the print head is MMC
Since it is BK, formats other than those shown in FIG. 19(D) require color conversion. This is explained in the 20th
In the figure, the RGB format shown in ■ first converts RGB to MMC.
, and then generate BK and a new MMC from the MMC. The reason for creating this new MMC will be described next.

BK data is Y=M=C=1, so when expressing black, if you use Y, M, and C as input data, black will be B.
K.

Since it is printed with all Y, M, and C inks, BK
The Y, M, and C portions of the dots that are printed/printed must be deleted.

Since BK data is added to the RGBBK format (2), only RGB needs to be converted to MMC.

For the MMC format (2), it is only necessary to generate a BK data and a new MMC.

As explained above, by supporting 3 FM data formats and 4 types of color specification modes, it has become compatible with various systems.

<Functions of MC4> MC4 uses DMAC (Direct Memory).
It has the function of reading the interface data 14, writing it to the memory 5, and executing vertical/horizontal conversion and nine-color conversion. An overview of the functions is listed below.

IFR mode...Write interface data to memory CC mode...Execute color conversion (MMC-BK) HV mode...Read interface data,
Immediately, DD mode for vertical/horizontal conversion...reads the interface data,
CD mode that does not write to memory... CDHV mode that writes fixed data in MCJ to memory... IFRI mode that converts fixed data in MC4 vertically and horizontally... HVI mode that writes inverted interface data to memory ...The data obtained by inverting the interface data is converted vertically and horizontally, and each mode will be explained in detail later.

<Description of inside of MC4> As mentioned above, MC4 has a DMAC function. This is a function executed by BA450 in FIG. 2, and stops the operation of MMPU3. This is an operation that must be performed in order for MC4 to start operating.
Furthermore, this function is mostly omitted in the following explanation and timing charts. The operation of BA450 will be explained in detail below.

The MC 4 of this embodiment writes data from the interface unit 6 into the memory 5. Or when reading/writing other various types of memory data, the MMPU 3 must be stopped and the address bus 14b and data bus 14 shown in FIG. 1 must be placed in a free state (tri-state state).

As a means of achieving this, we use a 16-bit MPU manufactured by Motorola.
(M68000), this color recording device uses
It is possible to obtain said state by the method shown in FIG. When the MC4 is ready for operation, the operation is started by an interrupt from the interface unit 6 (not shown) or by writing a command from the MMPU3 to the C0MR413. In FIG. 3, for example, when the MC4 starts operating by writing a command, the MC4 first writes *B.
This is a response signal from MMPt13 with R set to LOW*
Wait until BR becomes LOW. *When BR becomes LOW, the address bus 14b and data bus 14 are released, so both addresses and data are placed under the control of the MC4. Therefore, the MC4 starts operating at the same time as *BGA indicating that the operation is being executed is turned LOW. When the operation is finished, MC4 *
Set BGA to HIGH and pass address and data bus management to MMPU3.

[ADRC415... Address counter] A in Figure 2
The DRC415 specifies the address of the target memory, and is composed of a 16-bit counter, and is configured from addresses A1 to A1.
A has a day, ie a variable range of 64 words.

Since the memory 5 has a data width of 16 bits, the lowest address AO is not normally required, as shown in FIG.
The MC4 is equipped with a counter for Ao. A
The DRC415 has a variable increment amount depending on the settings from the MMPU3, and its biggest feature is that it can set an increment amount of +3 and allows control of both 8 and 16-bit interface data widths, so the same increment amount can be used. However, the increment amount of ADRC 415 is different.

FIG. 21 shows a method of storing input data in the memory 5 when the interface bus width is 8 bits and the input data format is 24 bits vertically.

As shown in FIG. 23, as can be seen from FIG. 17, storing manual data in order in the memory 5 is the easiest form to process, including control during printing, so the increment amount of ADRC 415 is If set to +1, the change in address will be n, n+1 . . . if n is initially set. n+2.
n+3... On the other hand, if the human input data format is 8 bits vertically, the input data shown in FIG. 21 is stored in the memory 5 intermittently as shown in FIG. To do this, if the increment amount of the ADRC 415 is set to +3, the output address will be n, n+3°n+6, . . . , and the result will be the same as in FIG. 22. When the increment amount of ADRC415 is set to +1, comparing when the interface bus width is 8 bits and when it is 16 bits, when it is 8 bits, the relationship between the input data in Figure 21 and the memory result in Figure 23 becomes 16 bits. When it is a bit, the input data shown in Figure 24 and the memory result shown in Figure 25 are obtained.As can be seen from Figure 25, the address output of ADRC415 is n, n+2.
．． n+4... howl.

Increment amount other than the above description +2. +4...is...
This is to be able to cope with changes in the number of elements in the head used for drawing. Note that +3 increments are effective only when using an 8-bit interface, and the configuration is such that when the bus width is 16 bits, the amount is automatically increased by +1 increments.

The above operation will be explained with reference to FIG.

PT810 is "1" when the increment amount is +3, "O" otherwise, PO312 is "1" when the increment amount is +3.
BW811 is a signal indicating the interface bus width.
'' is a signal that becomes 0 when it is 16 bits.802,8
03 is a binary counter and 801 is a ternary counter, but unlike a normal ternary counter, 0→1→2→0→
Instead of changing as 1..., it changes as 0-P3→2→1-0-..., and a carry signal (not shown) is always supplied to the upper counter (not shown) when counting up from 0 to 3. As a result, if the initial value is O, the lower 3-bit address changes from O-3 → 6 → 9...
When the initial value is 1, the sequence becomes 1 → 4 → 7 → A, etc., and when the initial value is 2, the sequence becomes 2 → 5 → 8 → B, etc. now,
When the interface bus width is 8 bits and the amount of change is +3, PT=1. Since BW=1, AND gate 816
The output 816a becomes "1", and the address signal Ao 8
14. A1815 has the output 80 of the ternary counter 801.
1a and 801b are output. If the amount of change is +3 and the interface bus width is 16 bits, BW = O
Therefore, AND gate 816 is prohibited, so 8
16a becomes “θ”, and from the AND gate 813, 80
2a and 803a are output to outputs 814 and 815. Also, since PO812=O, but PT=1, the AND gate 808 is enabled, and the binary counter 80
3 is incremented. As a result, when the amount of change is +3 and the interface bus width is 16 bits, the mode is automatically set to +1 and the address signal Ao 814 does not change at all.

Next, when the amount of change is +1, since PT810=O, the AND-OR gate 81
3 selects 802a and 803a. Since BW811=1 when the interface bus width is 8 bits, the operation of binary counters 802 and 803 is as follows.
02 is incremented and AND gate 806 is the carry signal of binary counter 803, so 802
When the binary counter 802 is incremented when a is "1", the binary counter 803 is also incremented at the same time. When BW811=O, that is, when the width is 16 bits, the AND gate 805 is prohibited, so the binary counter 802 does not change, but the AND gate 807
is enabled, so the binary counter 803 is incremented, resulting in n, n+2 . ...is obtained.

<BR414...Bank register> The color recording device has color memory divided into blocks. FIG. 8 is an explanatory diagram of this, and each color represents the address signal A1.
7-A23. BR414 in Figure 2
consists of four 7-bit registers, each of which can be set independently.

However, the Y bank must be set to #1, M to #2, C to #3, and BK to #4.

The reason for this is that the conversion order is fixed during the color conversion operation.

The C0MR413, which will be described later, has bits for selecting BR41 and 4, but the register numbers pointed to by these bits correspond to the number of the BR414. Therefore M
MPU3 sets all BR414 at the time of initialization, and if you do not change it after that, even if you make a mistake in setting the lower address of Al-Azs when accessing memory using MC4, the address part of BR414 will not change. It has the advantage that the contents of the memory other than the one selected will never be destroyed. Furthermore, by having four BR414s, even if there is only one tree of lower address registers, there appear to be four address registers, which is extremely useful.

<C0MR413...Command register> C in Figure 2
0MR413 is a 16-bit register, and MMPU3 inputs data to this C0MR413 i! By inputting F, commands are given to set the operation mode and start the operation. Its contents include 4 bits for operating mode setting, 2 bits for selecting interface bus width, 2 bits for selecting BR414, and ADRC.
415 bits for setting the increment amount, 4 bits for setting the last current to set the bit position of the target memory during vertical/horizontal conversion, and 1 bit for starting the operation.

The instruction decoding circuit ID430 in FIG. 2 receives the information from the C0MR413 and starts control according to each operation mode.

<LC412...Length counter> Figure 2 LC41
2 is a 16-bit counter that sets the number of reversals, and when one transfer is completed, it is decremented by 1 and the LC41
When all the contents of 2 become O, set the end bit 412a to 1'
to notify the ID 430 of the end of the operation.

Although the LC412 is a down counter in the above explanation, the internal circuit of the MC4 uses an up counter in order to simplify the circuit.

Therefore, in order to match the actual setting number and the number of transfers, MC
4 is ID4 when LC412 is selected by MMPU3
30 outputs a chip select signal 823 in FIG.

The chip select signal 823 is sent to the ninth chip by a circuit not shown.
When the inversion control signal 430a is set to "1", the invert circuit 416 inverts the input data 401 and outputs the data 41.
6b to the input terminal of the LC412 in FIG.

The LC 412 takes in the output data 416b inverted by the chip select signal 823. With this circuit, MM
When PU3 writes the transfer number 1, the output of LC412 is '
FFFE'. The circuit that detects the end of transfer is the second one.
8 As shown in figure 8, the end state detection gate 8 of Antogame 1.
21, all the outputs of the LC 412 are connected to the input. As a result, the transfer ends when all inputs are "1", that is, when 'FFFF' is detected. From this, if the above 'FFFE' is set, LC4
12 is counted up by the count-up signal LCP825, and the output becomes 'FFFF', which means that the transfer ends with one increment for the set transfer number 1.

After the power is turned on, the LC controller 412 is required to be in a transfer completed state, that is, all outputs are 1', for fail-safe purposes. However, even if LC412 has a clear terminal, the LC
When 412 is cleared, all outputs become "0", so in this embodiment, the transfer end state is not indicated. Therefore, in this embodiment, by adding the latch 820 shown in FIG. 28, it is possible to enter the transfer end state after power is turned on. It is an OR gate 822 to the output of the end state detection gate 821.
and the latch 8 is connected to one input of the OR gate 822.
20 output signals 820a are connected. This output signal 82
Since 0a becomes "1" with the clear signal 824, the output signal 822a of the OR gate 822 also becomes "1", so LC4
No matter what state the contents of 12 are, it indicates the end state. When the latch 820 then assumes that the LC 412 is in the selected state, that is, when the MMPU 3 writes to the LC 412, the counter set signal 823 becomes 0, so the output signal 820a becomes "0", and at the same time, the data 416b is set in the LC 412.

As explained above, a fail-safe circuit can be easily completed by simply inserting one stage of latch, and the LC412 can be an up-counter without a clear terminal, which helps reduce the number of gates when converting this example into an IC. It is clear that it will make a significant contribution.

(Margin below) Each operation mode will be explained below.

[Write interface data to memory] (IF
R mode) This is the most basic operation of the MC4 of this embodiment.

The operation of loading the interface data 15 from the interface unit 6 of FIG. 1 into the memory at the address set in the ADRC 415 inside the MC 4 will be described.

FIG. 5 is a timing chart, and FIG. 6 is an operation flowchart, and the explanation will be based on these.

In both FIG. 5 and FIG. 6, explanation of the portion of returning the MMPU 3 to the stopped state or to the operating state is omitted.

In FIG. 6, in step S61, DRQlol, which is an interrupt signal from the interface unit, goes high.
After detecting that the address bus 14b and data bus 14 are under the control of the MC 4, the contents of the BSEL 417 and ADRC 415 in FIG. 2, that is, the target memory address, are output in step S62. In step S63, the *IFR 106 is set to LOW in order to subsequently output the data stored in the interface unit 6 to the data bus 14 in FIG. In step 584, if the operation mode is IFH, the process proceeds to step S65.

The case when the mode is not IFR, that is, the DD mode will be described later. In step S65, the RW105 signal indicating the read/write status is set to LOW, and the *AS104 indicating the address strobe is also set to LOW. In step S66, the process branches depending on whether the bit width of the interface data 15 is 8 bits or 16 bits.

Now, assuming that the width is 8 bits, the process advances to step S67.

In step s7, it is determined whether the valid data on the data bus 14 is the upper 8 bits (Ds to Dz5) or the lower 8 bits (Do
~D? )+UDS102 and *LDS103 indicating the strength
Output. Based on these two signals, the memory 5 determines the data to be fetched. At this time, since the ADRC415 only has addresses 1 (A1) to 15 (A15) L/, a flip-flop for address 0 (Ao) (not shown, address *UDS according to the value of (see counter explanation)
, *LDS is determined. Step S68 is the final step of the memory write cycle, *As104, *
UDS102. *RW105. *1. At the same time when all FRs 106 are set to HIGH, the address bus 14b and data bus 14 are disconnected in order to transfer the management rights of the address bus 14b and data bus 14 to the MMPU 3, and the process ends.

Next, we will explain when the bus width of the interface data is 16 bits, but before that we will explain the case where the bus width of the interface data is 16 bits.
The switching operation for 16-bit width will be explained. When the interface data 15 is 16 bits wide, the data on the data bus 14 is the same as the interface data 15, but when it is 8 bits wide, the data on the interface data 15 is Do-D7 (lower 8 bits) of the data bus 14. Therefore, in order to write to the memory at an odd address (Ao value 1), the same information as the lower 8 bits must be given to the upper 8 bits of the data bus 14. This is realized in FIG. 4, where the lower 8 bits of the data bus 14 are always supplied to the lower 8 bits of the internal data bus IDo-1a (indicated by 401) of the MC 4 via the buffer 14e. However, while operating in this mode, I
Do-15 is not used inside MC4.

Now, when the data bus width is 8 bits, the data bus 14
The upper 8 bits of the data bus 14 are connected to the B input of the data selector 108, and the lower 8 bits of the data bus 14 are connected to the 8 bits. When the data bus width is 8 bits, BW811 is “
1'', the output Y of the data selector 108 is
Eight people's power data appears. Since the buffer 14C has a three-state control terminal, the buffer 14C is enabled when RW811 is "1", so the same information as the lower 8 bits appears in the upper 8 bits of the data bus 14. Similarly, when the data bus width is 16 bits, BW81
Since 1 is "O", the buffer 14C is disabled, so it has no effect on the upper 8 bits of the data bus 14, and the upper 8 bits of IDo-15 are the upper 8 bits of the data bus 14. The same data as the bit is output.

By having this function, which is an embodiment of the present invention, when the memory data bus width is 16 bits, the output interface data 15 of the interface unit 6 in FIG. 1 is composed of 8-bit wide data lines. Also, 16
Even if the data width is bit width, the MMPU 3 only sets the data width of the interface to the MC 4 once and is not concerned with the rest, and the interface data 15 is written to the memory 5 in an orderly manner, so the data management method is becomes very easy.

Next, we will explain the 16-bit data width in IFR mode in the sixth section.
In the figure, steps 361 to 66 are the same as in the case of the 8-bit data width. The difference is that step S66 branches to step S69, and in step S69, since the data width is 16 bits, *ID5102. *This is to set both LDS103 to LowW. The operation is completed by proceeding to step S68 after step S69. FIG. 5 shows the above explanation in terms of timing.

[Impair reading of interface data] (DD mode) This mode is a function that merely reads the data in the interface unit 6, but does not write it anywhere in the memory. To explain using the flowchart in FIG. 6, step S
Steps 61 to 64 are the same as the IFR mode, and step S6
4, the process branches to step S68.

This means that the signals *AS, *UDS, and *LDS are necessary for reading data into the memory 5.

This is an operation mode in which no RW is output, that is, no writing is performed.

This function is very effective in the following cases.

That is, when the host CPUI sends print data beyond the printable range of the color recording device 2 (see Figure 1), the color recording device 2 must discard the excess data, but this operation is handled by the software MMPU 3. It takes a very long time to process with this control.

At this time, if this function is used, the MMPU 3 only needs to set the command and the number of transfers to the MC 4. Therefore, the overhead between reading software interface data and other jobs is significantly reduced.

[Color conversion] (CCD mode) Y (yellow),
BK from three color data of M (magenta) and C (cyan)
The CC mode generates (black) data. Second
7 and 8. Before that, the color conversion generation formula used in this example will be described as follows: BK=Y-M-C Y'=Y-BK M'= M-BK C'=C-BK (y', ', c' are data of Y, M, and C after color conversion).

FIG. 8 shows the structure of storage addresses for each color data in this embodiment. Address signals A17 to A23 separate Y, M, C, and BK, and address signals Ax-Axe
(AO does not exist because the width of the data bus is 16), each word data is accessed. A point to be noted in this configuration is that the starting addresses of each color data (only the range indicated by A1-Ale) must be the same.

The commands and data sent from MMPU3 to MC4 in FIG. 1 include start address data to ADRC 415 in FIG. 2, number of words transferred to LC 412, B
Setting the data of bank #1 (Y data memory), bank #2 (M data memory), bank #3 (C data memory), and bank #4 (BK data memory) to R414, and finally color conversion to C0MR413 It is a command.

After receiving the color conversion command, the MC4 transfers the address bus 14b,
When the data bus 14 comes under the control of the MC 4, color conversion starts. FIG. 7 is a timing chart showing the execution state, and At-A23 is an address signal, especially AX7-A
23 is the upper 7 bits of bank address A17-A2
#n in 3 is the bank number. This is the above BR
Indicates that data corresponding to bank #n set to 414 is output, and n of AX-A1 B is ADRC415.
Indicates the data set to . Also, I of data Do-15
Or 0 indicates the direction of data, ■ is from memory 5 to MC4
to, 0 indicates the transfer direction from MC4 to memory 5, *A
S, *UDS, *LDS, and RW are all signals output by the MC 4, and the memory 5 uses these signals to control data input or output.

The color conversion procedure for one word will be explained step by step with reference to FIG. In step S71, the address outputs bank #1 (Y data memory 501 in FIG. 8 is selected),
The Y data is taken into the DR410 in FIG. Step S7
2, output bank #2 (M data memory 5 in Figure 8)
02) and imports the M data into the DR411 in FIG. 2. At step 573, the AND circuit 41 is
8, DR410 and DR411 are ANDed, and the ANDed data is taken into DR411. In step 574, bank #3 is taken into the output (C data memory 503 in FIG. 8) L, DR 410. Step S7
5, the operation is exactly the same as step S73, but as a result, Y*M*C, that is, BK data remains in the DR 411. In step S78, bank #4 (BK data 504 in FIG. 8) is output and written into the memory.

In step S77, new Y and M are set.

As a preliminary preparation for generating C data, the BK data is inverted and rewritten to the DR 411.

This means that the ID430 sets the inversion signal 430a in FIG.
By supplying the data to the INV416 with a value of "0", the data on the internal data bus 401 is inverted and becomes the power of the DR411. This is explained in FIG. 9. In the case of non-inversion, the inversion signal 430a is "0" Therefore, the internal data 401 is supplied to the DR 411 without being inverted, and at the time of inversion, the inversion signal 430a becomes "1", so the internal data 401 is inverted and supplied to the DR 411. Through this operation, the inverted signal is It can be easily obtained.In step S78, the Y data is taken into the DR410.

In step S79, the AND signal of D1410 and DR411, that is, new Y data, is written into the Y data memory 501. In step S80, M data is taken into DR410. In step S81, DR410 and DR411
The AND signal, ie, the new M data, is written into the M data memory 502. In step S82, the C data is transferred to the DR410.
Incorporate into. In step S83, DR410 and DR4
11 AND signal, ie, new C data, is written into the C data memory 503. At this step, the color change of one word is completed, so add 1 to ADRC415, and then add 1 to LC41.
Subtract 2 by 1. As a result, if the content of LC412 is not zero, the next word conversion is executed as shown in FIG. 7, and if it is zero, the process ends.

As described above, according to this embodiment, the color conversion of one word (two bytes) is performed without interruption to the memory 5, so it can be seen that it can be executed much faster than conversion by software.

[Vertical/horizontal conversion] (HV mode) This mode is used when the data format from the host CPUI is a raster image format, as shown in Figure 10 (a).
) to (C) are diagrams comparing manual data from the host CPUI and the contents of the memory after conversion. Figure 10(a) shows the manual data (data sent from the host CPUI) when the interface bus width is 8 bits, and Figure 10(b) shows the contents of the memory 5 after execution of this mode.

It is shown in (C). In both FIGS. 10(b) and 10(e), the shaded areas indicate that the contents have not changed at all from before the execution of this mode. FIG. 10(b) is the result of executing MSB first conversion, and FIG. 10(e) is the result of executing LSB first conversion, and the differences between the two will be described later.

Here, the HV mode will be explained with reference to FIG. 2, FIG. 11, and FIG. 12 on the premise that MSB (D7) first conversion is performed. Note that the part for importing the interface data 15 is omitted, and it is assumed that the data in FIG. 10(a) is stored in the DR 410.

In Figure 11, BCNR421 is an octal binary counter,
PSMX of PS420 is an 8→1 multiplexer, Y is a positive logic output, BCSL of BC419 is a 4→16 data selector, and BCA to BCA32 are AND gates.

If you explain along the map of East 12, the address at the start of operation is m.
%LD=1 (indicating MSB first conversion), when the bit designation signal 430b of the target memory in FIG. , Dl410 data is the first
In the example shown in FIG. 0 (b), Dl of the memory is specified.

In step 5121, the data at address m is DR
411.

In step 5122, the first bit obtained by parallel-to-serial conversion of the output of DR411 appears at 420a in FIG.
410 by replacing the output of 0 with Dl of 410a in FIG.
Data other than D1 of a is written to the memory at address m without being changed at all. In the above operation, BCNR421 is all “0”
”, and LD = 1, so PSMX inputs A and B
, C are all “1”, so PSMX output Y4
Dl of the output 411a of the DR 411 is output to 20a. On the other hand, the output of BC3L is B=C=D when the input is A=1.
= O, so only BCSLI is "0" and everything else is "1", so the output 410a of DRl 40 is B
CAI, BCA5°BCA9. . . . Since the BCA 31 is enabled, the same data as 410a is output to the internal data bus 401 except for Dl. BCA3. B.C.
Regarding A4, since BCAL1=O, BCA3 is disabled and BCA4 is enabled, so the signal 420a, that is, the MSB of 411a, is output to the internal data bus 401. This results in the same result as the address m in FIG. 10(b).

At the end of this step BCNR421 and ADRC41
Prepare for the next step by adding 1 to 5.

As a result, address At-AL8 is m+1, BCN
Output of R421 421a=1.421b-421c=O
1, that is, inputs A and B of PSMX.

C becomes A-0, B=C=1.

In step 123, data at the address indicated by Al-Aha is taken into the DR 411.

Step 124 is the same as step 122, except that the content of PSMX(7) output Y420a is selected by PSMX manual input A, B, and C (D6 is selected in step 124).

Do the above in odd number steps (121, 123°125...
), even steps (122, 124°126...)
The same operation as LC4 is repeated in step 5136.
Since the operation of decrementing 21 by 1 is added and the conversion is completed at step 136, the operation of MC4 itself is completed and MNPU
The management of the address bus 14b and data bus 14 is transferred to the address bus 14b and the data bus 14.

The above explanation is based on the data stored in DR411.
This is a mode in which conversion is performed with B (D?) at the beginning, but a feature of this embodiment is that it is provided with a mode in which conversion is performed with LSB (Do) at the beginning.

To implement this method, when the MMPU3 sends a command to the MC4, a switching command for MSB/LSB is provided (or by an external terminal of the MC4), so that the LD signal shown in FIG. By setting it to ``O'' in the previous case, the selection input terminal A of PSMX.

B and C become D by inverting and non-inverting the output of BCNR421.
It is determined whether the selections are made in order starting from l or Do.

By providing this function, the raster format from the host CPUI becomes 2FFFI, so please use it as a processing method within the host CPUI! This has the advantage of being selectable in -41.

Further, in the above explanation, the interface bus width was 8 bits, but a feature of this embodiment is that a 16-bit bus width can also be selected (see IFR mode). Although the specific means are not shown, taking FIG. 11 as an example, BC
This is realized by making the NR421 a 4-bit counter and changing the PSMX from the 8→1 multiplexer in FIG. 11 to the 16→1 multiplexer.

As described above, according to this embodiment, vertical and horizontal conversion of 1 byte, 8 bits can be performed in a short time of 16 steps. now,
If one memory cycle is 250ns, then 250nsX
It will end in 16=4ns.

[Fixed data writing] (CD, CDHV mode) This example operates as a simple MAC, but the D
It has functions that MAC does not have.

These are fixed data write modes, namely CD mode and CDHV mode.

In this mode, when data is written to DR411 in MC4, data in DR411 is continuously transferred to memory 5 for the number of transfers.
This is the operation of writing to.

The CD mode has exactly the same operation as the IFR mode, and the CDHV mode has the same operation as the HV mode except for the following points.

The difference is that the target conversion data is data written to DR411 in CD and CDHV modes, and interface data in IFR and HV modes.
In the HV mode, the number of transfers set in the LC 412 is continuously executed. This is explained in Figure 13 (
a).

(b) and FIG. 13(a) are explanatory diagrams of IFR, After completion, the bus management right is passed to MMPU3. One byte (
or 1 word).

FIG. 13(b) is an explanatory diagram of the CD and CDHV modes.
When MPU3 writes a command to MC4, MC4
The processing is performed continuously for the amount set in the LC 412. Therefore, if the number of transfers is large, the time until the MMPU 3 becomes operational becomes longer.

14(a) and 14(b) show the contents of the memory 5 after executing the CD and CDVH modes, respectively.
(b) It is very effective when used to clear the memory as shown in the figure. To write a staggered pattern as shown in Figure 15 to the memory 5, 1. Set the Ni start address to n. 2. Set the increment amount of the address counter to +2. 3. Set the number of transfers N to the length counter. 4. Set the DR411. :'
Set 1010101010101010° 5: Send CD command: (M, C4 executes CD mode) 6: Set start address to n+1 7: Set address counter increment to +2 8: Set transfer number N to length counter 9:X'010101 to DR411
Set 0101010101 10: Send CD command; (Execute CD mode) There is an advantage that a staggered pattern can be created at high speed simply by performing the following control.

[Data inversion mode (IFRl, HVI mode) Both modes perform the same operation as the IFR and HV modes, but this mode differs from the IFR and HV modes in that the interface data 15 is inverted and used.

To explain the I FRI mode in Figures 9 and 29,
In the IFRI mode, the signal 430a in FIG. 9 is set to “1”.
” and input the interface data 15 into the DR441. Since the signal 430a is “1”, the inverted data of the internal data bus 401 is stored in the DR411. Next, when *IFR in FIG. 29 is set to “1”, the data Since the bus 401 is in a floating state, the MC4 outputs the contents of DR411 to the external data bus 14, and also sends control signals *LIDS, *LDS, *AS, and R to the memory 5.
Output W and exit.

In HVI mode, the only difference from HV mode is that 4038 in Figure 9 is set to "1" and the inverted interface data 15 is loaded into DR411, as in IFRI mode, and everything else is the same as HV mode. be.

The advantage of the zero mode is effective when converting RGB data to YMC data. This is shown in Figures 19 and 30.
To explain using figures, Fig. 30 (A) is different from Fig. 19 (
The data format of A) and FIG. 30 (B) explain an example of the data format of FIG. 19 (C). Since the data format of FIG. 0M is bank #1 in bank #1 of
2, C may be stored in bank #3. This is the 30th
As explained in Figure (B), when setting the IFR mode, select the link number #1. #2゜It is sufficient to perform in the order of #3. On the other hand, the data format in Fig. 19 (A) is RG.
Since it is in B format, it is necessary to convert it to MMC. For this purpose, a conversion expressed by the following equations is performed: Y=notB M=notG C=notR. This is achieved by IFRr or HBI mode, and the first data block is R, so bank #3
, the next one is M, so select bank #2, and the last one is B, so select bank #1. Therefore, MMPU3 has software related to color conversion that is M.
It is very efficient because it is only necessary to set the command, address, and number of transfers for C4.

After this, the aforementioned CC mode is used to convert YMC to YMCBK.

<Auto refresh function> If the printable area of this color recording device is 8 inches and the horizontal dot resolution is 200 dpi (dots/inch), the memory capacity required for one line is 8 (inches) x 2.
00 (dp 1) x 24 (element/head) x
4 (number of heads) = 153,600 bits, and if this is expressed in the number of bytes, it becomes 153,600÷8-19.2 KB. With this level of capacity, it is natural to use static RAM.
However, in another application example, assuming a device with a printable area of 15 inches, a dot resolution of 400 dpi, and 128 elements/head, the memory capacity would be 384 KB, so a dynamic RAM may be used as the memory. Dynamic RAM has the disadvantage that memory contents change unless it is refreshed periodically. The refresh circuit creates a refresh signal under the control of the MMPU 3, or detects free time inside the memory 5 between accesses from the MMPU 3 and creates a refresh signal. However, in this embodiment, especially in color conversion, the color conversion is executed within the cycle time limit of the memory 5, and since it is impossible for the MMPU 3 to interrupt the execution while it is being executed, there is a possibility that refreshing will not be possible. I'm coming.

To compensate for this drawback, the MC4 is provided with an ARI signal (not shown) as an external terminal, and when the ARI signal is "1", the CC
Auto-refresh is executed only in mode, CD, and CDHV mode. The reason why auto-refresh is not executed in modes other than those described above is as shown in Figure 13 (
In a), the time during which the MC4 manages the address bus 14b and the data bus 14 is less than 1 μs, and the time is 1 μs.
This is because control of the address bus 14b and data bus 14 is temporarily returned to the MMPU 3 every time the process is executed.

On the other hand, in CC, CD, and CDHV modes, the 13th
As shown in Figure (b), for a long time the address bus 14b
This is because the MC4 manages the data bus 14. This will be explained using FIG. 7 and FIG. 31, taking the CC mode as an example.

Figure N7 is an example when auto-refresh is not executed, and step n in the CC mode is a repetition of steps 71 to 83.

On the other hand, when auto-refresh is executed, one cycle of dummy steps is inserted between step S83 and the next step S71, as explained in FIG. 31, and at this time a refresh pulse *RF is output. At this time *AS, *LD
S.

All RSs are "1". A1-A23 in FIG. 31 is the MC that outputs exactly the same signal as in step S83.
4 because it does not have an address counter for refreshing. Therefore, when the memory 5 receives *RF, it executes refresh using its own address counter.

(LC latch, ADRC latch) MM when storing data in the MMC data format shown in Figure 19 (C) in the memory 5 using IFR mode
The outline of the commands etc. that the PU3 sends to the MC4 has already been described in Figure 30 (B), but to explain this in more detail, there are three processes: address counter setting, length counter setting, and command setting. The IFR mode is executed by repeating this three times, but as explained in Figure 19 (C), the length counters are data of the same length for Y, M, and C, and the contents of the address counters are also color converted. For reasons of logic, data must be stored from the same address, so it is necessary to set the same data. Therefore, LC412, ADRC
If a latch is installed in the data manual section of 415, ADRC41
5. Settings for LC412 only need to be done once MM
Processing on the PU3 side is greatly simplified. This is explained in FIGS. 32 and 33. Lc412, ADRC
415 only have different functions and are the same in terms of data settings, so only the LC 412 section will be described. FIG. 33(A) is an address assignment table for registers and counters before a latch is provided, and for convenience of explanation, $1 is left blank. Now when setting data to LC412, MMPU
When 3 is written to address xxxx2, the data at that time is stored in the LC 412.

FIG. 33(B) is an address assignment table when a latch is provided, and although it is not changed from FIG. 33(A), the circuit is different. That is, a latch 831 is provided in front of the input section of the LC 412 in FIG.
Take in b. When MMPU3 writes data to address xxXX2 in FIG. 33(B) in order to set data in LC412, the clock signal 833 of latch 831 in FIG. 32 becomes "1" and latch 831 writes data 41.
Take in 6b. Subsequently, MMPU3 is C0MR41
When data is written to LC4, the signal 834 becomes 0''.
12 is a latch 831 and takes in data. With this circuit, it is only necessary to set data to ADRC 415 and LC 412 once before step 5311 in FIG. 30(B), and it is not necessary in steps 5312 and 3313.

It is obvious that the load on the MMPU 3 can be further reduced by implementing the circuit described above.

However, when the input data format is raster image data, MMC format, and 1 color data is 10
When it is 0 byte, as explained in FIG. 34, from receiving the input data to printing, in step 5341, the ADRC 415, that is, the start address setting is 0° in this example, and the LC 412 is 1 color data is 100. Since it is a byte, set it to 100.

In step 5342, the vertical/horizontal conversion HV mode is repeated 72 times. The color specification format for this is Y.

2 because it is M, C and the number of head elements is 24.
Since data is received 4 times, the number of vertical and horizontal conversions is 3x24.
This is because it becomes -72.

- In step 5343, the address and the value of LC412 are reset to execute the color conversion CC mode. ADR
C415 can be 0, but LC412 has input data of 10
Since 0 bytes were converted vertically and horizontally, as explained in Figures 10(a) and (b), the memory is multiplied by 8 in the horizontal direction and stored, so 100x8=800,800 is stored in the LC41.
Set to 2.

In step 5344, the CC mode execution step 53
In step 45, the process for one printing is completed after printing is executed, and the process proceeds to step 53.
41, but at step 5341, ADRC4
15. Specified values must be set for LC412.

A circuit devised to improve this point is shown in Figure 35.
As a result, after the first printing is completed in FIG. 34, instead of returning to step 5341, the process returns to step 5342, as shown by the dotted line. Due to this, MMPU
The software in No. 3 is further simplified. The method will be explained below.

Figure 33 (C) is an address allocation table when the improved plan is implemented. The difference from Figures 33 (A) and (B) is that $1 is the command register, $4 is the length latch, and $5 is the address latch. This is the point I made.

FIG. 35 shows an example of a circuit, in which the latch 831 in FIG. 32 is changed to a latch with a tri-state buffer, and the circuit changes from FIG. 32 to FIG. 35 by adding a tri-state buffer 830.

When the MMPU 3 selects the length counter $2 in FIG. 33(C), the signal 832 becomes "O" and the rebuffer 83
0 is enabled and the buffer section of the latch 831 is disabled, so the internal bus 416B appears at the input section of the LC412, and at the same time the signal 823 becomes "0", so the output 835a of the OR gate 835 also becomes "0". ,
The same data as 416b is taken into LC412.

When MMPU3 selects length latch of $4, signal 8
33 becomes "1" and the latch 831 takes in the data of 416b.The data taken into this latch 831 is
In order to transfer the data to the C412, the MMPU3 only has to select the $1 command register. At this time, the signal 832 is 1″
Therefore, the buffer 830 is disabled and the output of the latch 831 is enabled, so that the contents of the latch 831 appear in 8308, and as a result, the same data as the contents of the latch 831 is taken into the LC 412. The above relationship is shown in FIG.

The operation of FIG. 34 by this circuit is as follows: In step 5341, the start address is set in the $5 address latch, and the number of transfers, 100, is set in the $4 length latch.

In step 5342, the operation of setting the HV command in the $1 command register is repeated 72 times.

In step 5343, the start address is set in the address counter of $3, and the number of transfers, 800, is set in the length counter of $2.

In step 5344, CC is written to the command register of $0.
Set the mode and execute.

In step 5345, printing is executed, and after completion, step 5
Return to 342.

In the above explanation, there are two C0MRs 413, but in reality there is only one register, and it is designed to operate differently depending on the address.

As described above, the present invention has the effect of greatly simplifying the MPU software by applying it to a color recording device in particular, and furthermore, it has a large capacity because it executes interface data import, color conversion, vertical/horizontal conversion, etc. at ultra-high speed. A color recording device with high throughput can be realized even with data of

(The following is a blank space) [Effects of the Invention] According to the present invention, it is possible to provide a memory control circuit that stores manually input data in a memory in a data arrangement that matches the output element.

Furthermore, even when input data has a different bit arrangement, it is possible to provide a memory control circuit that stores the data in a memory in a data arrangement that matches the output element.

(Margin below)

[Brief explanation of drawings]

Figure 1 is a block diagram of the color recording device, Figure 2 is a block diagram of the memory control circuit, Figure 3 is a timing chart of the use of the memory control circuit data bus and address bus, and Figure 4 is 8-bit width/16-bit width. Switching circuit diagram, Figure 5 is a timing chart of IFR mode, Figure 6 is a flowchart of IFR mode, Figure 7 is a timing chart of CCD mode, Figure 8 is an addressing diagram of the memory control circuit, and Figure 9 is the inverter logic. Circuit diagram, Figures 10 (a) to (c) are HV mode explanatory diagrams, Figure 11 is an HVi conversion circuit diagram, Figure 12 is a timing chart of MV mode, and Figure 13 (a) is an explanation of IFR and HV modes. 13(b) is an explanatory diagram of the CD and CDHV modes. FIG. 14(a) is a memory state diagram after executing the CD mode. FIG. 14(b) is an execution state diagram after executing the CDVH mode. Figure 15 is a diagram of the staggered pattern formation state, Figure 16 is a comparison diagram of input data and output results in Lester format, Figure 17 is a comparison diagram of input data and output results in vertical 8-bit image format, and Figure 18 is a comparison diagram of input data and output results in vertical 8-bit image format. Comparison diagram of input data and output results in vertical 24-bit image format, Figures 19 (A) to (D) are color specification format side ports, Figure 20 is a diagram explaining color conversion, Figure 21 is 8-bit wide image format. Input data diagram, Figure 22 is vertical 8
Fig. 23 is a storage state diagram when formatting 8 bits manually and 24 bits vertically; Fig. 24 is a diagram of 16 bits wide input data; Fig. 25 is a diagram of 8-bit width input data
Storage state diagram for vertical 24-bit format with bit width input, Figure 26 is a partial circuit diagram of the address counter, Figure 27 is an address designation diagram of the memory control circuit, Figure 28 is a length counter circuit diagram, and Figure 29 is a diagram of the address counter. Timing chart of I FRI mode, Fig. 30 (A) is a flow chart of I FRI mode, Fig. 30 (B) is a flow chart of IFR mode, Fig. 31 is a timing chart of auto-refresh, Fig. 32 is a latch of the length counter. Circuit diagram, Figure 33 (A) to (C) is an explanatory diagram of commands to the memory control circuit, Figure 34 is a flowchart of the mask MPU, Figure 35 is a control circuit diagram of the length counter and latch, Figure 36 is the length counter and latch control circuit diagram. In the figure, 1... host CPU, 2... color recording device, 3... master MPU, 4... memory control circuit, 5
...Memory, 6...Interface unit, 7
...Sub MPU, 8...Print head, 9...Paper feed motor, 10...Carriage motor, 410°41
1...Data storage register, 412...Length counter, 413...Command register, 414-...
Bank register, 415...address counter, 41
6... Inverter logic, 417... Bank selector, 418... AND logic, 419... Bit change, 420... Parallel to serial conversion circuit, 421...
Bit counter, 430... Instruction decoder, 440... Micro sequencer, 450...
It is a bus arbiter. Fig. 5 Fig. 9 Fig. 13 (CI) Fig. 13 (b) Fig. 17 Printed sword system Yoshika old drawing 11f + Uto force result Fig. 19 (A) Fig. 19 (8) Section 19 ( C) Fig. 19 (D) Fig. 20 Fig. 21- Fig. 22 Fig. 23 Cause 24 District Fig. 25 Fig. 30Im (A) Fig. 30rIA (8) Q
0 0 ===---00------δ 〇 - Ku No. 31ffl No. 32 rIA No. 33 rlA (A) No. 3311 A (B) No. 33 rlA (C)

Claims (12)

[Claims] (1) A memory control circuit that controls a memory for storing image data, including a vertical/horizontal conversion means for vertically/horizontally converting the arrangement of data, and storing input data in the memory in a data array that matches the columns of output elements. -Memory control circuit featuring: (2) The memory control circuit according to claim 1, wherein the memory is controlled by a direct memory access method. (3) The memory control circuit according to claim 1, wherein the vertical/horizontal conversion means converts continuous bits of data into data at predetermined bit intervals. (4) The memory control circuit according to claim 1, wherein the input data is in raster format and the output element is a serial printer. (5) The memory control circuit according to claim 1, wherein data is controlled in units of 16-bit width. (6) The memory control circuit according to claim 1, wherein data is controlled in units of 8-bit width. (7) A memory control circuit that controls the memory for storing image data, which includes a first vertical/horizontal conversion means that converts the data arrangement vertically and horizontally from the most significant bit, and a first vertical/horizontal conversion means that converts the data arrangement vertically and horizontally from the least significant bit. a second aspect conversion means; a designation means for specifying whether the conversion is performed by the first aspect conversion means or the second aspect conversion means; and the first aspect conversion means based on the specification by the designation means. and said second vertical/horizontal conversion means, and stores input data in a memory in a data arrangement that matches a column of output elements regardless of the arrangement of bits. (8) The memory control circuit according to claim 7, wherein the memory is controlled by a direct memory access method. (9) The memory control according to claim 7, wherein the first vertical/horizontal conversion means converts consecutive bits from the most significant bit of data of a predetermined width into data with a predetermined bit interval. circuit. (10) The memory control according to claim 7, wherein the second vertical/horizontal conversion means converts consecutive bits from the least significant bit of data of a predetermined width into data of a predetermined bit interval. circuit (11) The memory control circuit according to claim 7, wherein data is controlled in units of 16-bit width. (12) The memory control circuit according to claim 7, wherein data is controlled in units of 8-bit width.