JPS62219045A - Lru control circuit - Google Patents

Abstract

PURPOSE:To control an LRU quickly with simple constitution by judging the last accessed area as the oldest area to output area information and updating identification information if information of an area to be accessed and area information read out from a tag memory coincide with each other in a comparator. CONSTITUTION:An actual address AY and addresses read out from tag memories 1-1-1-4 are inputted to comparators 3-1-3-4 and are compared with each other, and a pertinent buffer is accessed by an address AZ generated by an encoder 6 if they coincide with each other. If a coincidence signal is detected by the comparator 3-1, address data read out from a flag memory 2-1 is inputted as an address (y) of ROMs 4-1-4-4. An address (x) read out from flag memories 2-1-2-4 and the address (y) are inputted as address signals to ROMs 4-1-4-4, and new discrimination information obtained by updating identification information read out from flag memories 2-1-2-4 are generated.

Description

[Detailed Description of the Invention] [Summary] The present invention provides an LRU control circuit that performs control to detect and write to an area whose last access time is the oldest. A flag memory that stores identification information including whether the area was last accessed at the earliest time and the order of age, and an identification information update unit that updates the identification information stored in this flag memory. If the area information that is currently being accessed matches the area information read from the tag memory, the area information that was last accessed is the oldest and the identification information stored in the flag memory is updated. I try to do that.

[Industrial application field]

The present invention relates to an LRU control circuit that performs control to detect and write to an area that was last accessed at the oldest time.

[Problems to be solved by conventional technology and invention] In a computer system, the area where the buffer memory was last accessed is the oldest, and this detected area is determined to be the least accessed area and given priority. LRU (Least Recent)
ly Used) control circuit.

Conventionally, in this t, Ru111M1 circuit, in order to detect the area whose last access point was the oldest, a table was set up to manage the access point of the area, or a logic circuit was used to manage it. However, there was a problem in that the control became complicated.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides identification information including the oldest access point and the order of age for each area accessed based on the area information stored in the tag memory. a flag memory that stores
An identification information updating unit is provided to update the identification information stored in this flag memory, and when the area information currently being accessed matches the area information read from the tag memory, the area information is output and , the identification information stored in the flag memory is updated.

Means for solving the problems will be explained using the configuration diagram of one embodiment of the present invention shown in FIG.

In FIG. 1, tag memories 1-1 to 1-4 are used to write addresses (fil area information) of data stored in buffer memories (not shown).

The flag memories 2-1 to 2-4 store identification information for identifying how old each of the tag memories 1-1 to 1-4 belonging to each group was accessed.

The comparators 3-1 to 3-4 respectively compare whether or not the actually accessed address A'Y and the address read from the tag memories 1-1 to 1-4 match. It is.

The ROMs 4-4 and 4-4 store tables for updating identification information stored in the flag memories 2-1 and 2-4.

The encoder 6 generates an address AZ for selecting a block to access the buffer memory based on the match signals notified from the comparators 3-1 to 3-4.

[Effect]

The configuration explained using FIG. 1 is adopted, and when the buffer memory (not shown) is accessed, tag memories 1-1 to 1-4 are accessed at the same time. At this time, the actual address AY and the addresses (area information) read from the tag memories l-1 to 1-4, respectively, are input to the comparators 3-1 to 3-4 and compared. As a result of the comparison,
If there is a match, the corresponding buffer is accessed by the address AZ generated by the encoder 6. At this time, if a matching signal is detected by any one of the comparators 3-1 to 3-4, for example, the comparator 3-1,
Address data read from flag memory 2-1 (
t1m-specific information) is input as the address y of each ROM 4-1 to 4-4.

As a result, the address X read out from the flag memories 2-1 to 2-4 and the address y are input as address signals to each ROM 4-1 to 4-4, respectively. New identification information is generated by updating the respective identification information read from 2-4.

Each of the generated identification information is rewritten in a manner that updates the identification information stored in the flag memories 2-1 to 2-4.

As described above, when the address (area information) read from the tag memories 1-1 to 1-4 matches the address AY that is currently being accessed, the flag memory 2-
It becomes possible to rewrite the identification information stored in addresses 1 to 2-4 in an updated manner and output the address AZ for accessing the buffer memory.

〔Example〕

The configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 and 2.

In FIG. 1, tag memories 1-1 to 1-4 are used to write addresses of data stored in buffer memories, and flag memories 2-1 to 2-4 are tag memories 1-1 to 1-4, respectively. Comparators 3-1 to 3-4 store identification information for identifying how old the access was.
ROM 4, which compares Y and the addresses read from tag memories 1-1 to 1-4, respectively, to see if they match.
-1 to 4-4 are for storing a table for updating identification information, and an encoder 6 is for generating an address AZ for accessing the buffer memory.

Next, the operation of the configuration shown in FIG. 1 will be explained.

In FIG. 1, when a buffer memory (not shown) is accessed, tag memories 1-1 to 1-4 are accessed at the same time, and address data is transferred to a comparator 3, respectively.
-1 to 3-4, respectively. This input address data and address AY are compared, and if they match, a match signal is output. In the embodiment shown in FIG.
Consider two groups of buffer memories and four groups of tag memories 1-1 to 1-4 corresponding thereto. As a result of address comparison, for matching blocks,
With the address AZ generated by the encoder 6,
Buffer memory is accessed. At this time, flag memories 2-1 to 2-4 are provided for each block, respectively, for storing identification information for knowing how old each group was accessed. These flag memories 2-1 to 2-4 each contain 00 as initial data.
．． 01.10 and 11 are written in advance. Here, for example, if the address data read from the tag memory 1-1 matches the address AY and a match signal is output from the output of the comparator 3-1, then the flag memory 2
The data read from -1 is input as the address y of each ROM 4-1 to 4-4. At this time, the value of address y is OO'' (meaning that it was accessed at the earliest point).The addresses x of ROM4-1 to 4-4 are 00.01.10 and 11, respectively. Therefore, each output of the ROM 4-1 to 4-4 becomes 11.00.01 and 10 from the table shown in FIG. -4, and the data stored in the corresponding flag memories 2-1 to 2-4 is updated.In the same manner, the comparators 3-1 to 3-4 of any block are updated. The data stored in the flag memories 2-1 to 2-4 is updated every time the flag memories 2-1 to 2-4 output a match signal.As a result, the data stored in the flag memories 2-1 to 2-4 is OO. The block is
The oldest block is the one that was last accessed (
LRU control). Also, here, the comparators 3-1 to 3-
4 does not output a matching signal, the data (identification information) stored in the flag memories 2-1 to 2-4 remains unchanged by controlling to generate 11 as the address y. is maintained in the state of

As explained above, tag memory 1-1 or 1-
When the address data read from 4 matches the address AY that is currently being accessed, the flag memory 2-1 or 2-2 is associated with the address data.
Data read from 4 (00, 01, 10, 11)
is rewritten as an updated C, so to speak, and it becomes possible to output a predetermined address AZ corresponding to the matched block.

FIG. 2 shows an example of a table stored in the ROMs 4-1 to 4-4. As can be seen from the configuration shown in FIG. 1, the horizontal axis X in the figure indicates address data The vertical axis y represents one address data read from the flag memories 2-1 to 2-4 corresponding to the block that outputs the match signal in the comparators 3-1 to 3-4. Let X be the address y for this ROM 4-1 to 4-4.
This is input in a common manner as . As explained above, the address As shown above, 00.01.10.11 is initially stored in the flag memories 2-1 to 2-4, and when a match signal is output from the comparator 3-1 corresponding to the flag memory 2-1. , address X for ROM4-1
and address y are respectively "o6", and the address y is "o6".
Data 11" (indicating the latest state at the time of access) is read from M4-1 and written in the flag memory 2-1 as updated. At this time, data from other ROM4- The addresses X for 2 to 4-4 are 01.10.11, respectively, and the addresses y are 0O100, respectively.
00tonari, from this 8yen ROM 4-2 or 4-4.

The data ``O'', @01'', and ``10'' are respectively read and written into the flag memories 2-2 to 2-4 in an updated manner.Here, the access point is 0.
The new information is updated in the order of 0, 01.10.11. That is, “00
The point in time when `` is accessed is the oldest, and the point in time when ``11'' is accessed is the newest. Therefore, data is written to those corresponding to flag memories 2-1 to 2-4 in which 00'' is stored. LRU control is sufficient.

FIG. 3 shows a block diagram of another embodiment. This is because although the configuration shown in FIG. 1 uses four sets of flag memories 2-1 to 2-4, one set of these is a redundant bit.
Omitting the redundant set of flag memories 2-4 and using three sets of flag memories 2-1 to 2-3,
Instead, E○R5-1 and 5-2 are used for control. As a result, compared to the configuration shown in FIG. 1, one set of flags/-[-res 2-4 and one set of ROMs 4-4 are required, resulting in a simpler configuration.

FIG. 4 shows a configuration diagram of another embodiment. This is because although the configuration shown in FIG. 1 uses four sets of flag memories 2-1 to 2-4, one set of these is a redundant bit.
The redundant set of flag memories 2-4 is used to perform a parity check to improve reliability.

In this embodiment, the flag memories 2-1 to 2-4 are divided into 4 blocks, and 2 bits are allocated to each block, but the present invention is not limited to this. A number may be assigned to each.

〔Effect of the invention〕

As described above, according to the present invention, identification information including the oldest access point and the order of age is provided to each area accessed based on the area information stored in the tag memory. A flag memory that stores
An identification information update unit is provided to update the identification information stored in this flag memory, and if the area information currently being accessed by the comparator matches the area information read from the tag memory, By adopting a configuration in which the area is determined to be the oldest area and the area information is output, and the identification information stored in the flag memory is updated, LRU control can be performed quickly using a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is an example of a table stored in a ROM, and FIGS. 3 and 4 are block diagrams of other embodiments of the present invention. In the figure, 1-1 to 1-4 are tag memories, 2-1 to 2-4 are flag memories, 3-1 to 3-4 are comparators,
4-1 to 4-4 represent ROMs.

Claims (1)

[Claims] In an LRU control circuit that performs control to detect and write to an area where the last access was the oldest, the tag memory (1) stores information on an area to be accessed from the buffer memory; For each area accessed according to the area information stored in 1), there is a flag memory (2) that stores identification information including the oldest time of last access and the order of staleness; A comparator (3) that compares whether or not the area information read from the tag memory (1) matches the area information read out from the tag memory (1), and based on the comparison result by this comparator (3),
an identification information updating section (4) for updating identification information stored in the flag memory (2);
), the LRU control is characterized in that the LRU control is configured to output area information having the oldest access point and update identification information stored in the flag memory (2) based on the comparison results compared by the above. circuit.