JPH08241242A - Method and circuit for memory control - Google Patents

Abstract

PURPOSE: To partially rewrite data at a high speed with respect to the method and circuit for memory control which rewrite a part of data stored in a memory. CONSTITUTION: One additional data is provided per data unit, and the data unit is stored divisionally in continuous addresses of a data part memory, and additional data is stored in an additional part memory. In this memory system, additional data corresponding to the data unit is read out from the additional part memory by the first address access to this data unit in the data part memory and is held, and contents of additional data are updated on the outside of the additional part memory by following continuous address accesses to the data unit, and updated additional data is written in the original address of the additional part memory at the time of the last address access to the data unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control method and a memory control circuit for rewriting a part of data stored in a memory.

[0002]

2. Description of the Related Art FIG. 6 shows a configuration example of a communication card. The communication card 20 includes a bus controller 21, a parity RAM 22, a data RAM 23, a protocol controller 24, a CPU (central processing unit) 25, and the like. The communication card 20 is connected to the host computer 30, and the bus has a data width of 32 bits (D0 to D).
31). On the other hand, the data width of the bus in the communication card 20 is 32 bits between the bus interface 21 and the data RAM 23, but the protocol controller 24 and C
There are 16 bits between the PU 25 and the bus controller 2
1 and the lower 16 bits of the data RAM 23.

Therefore, 32 of the host computer 30
As for bit data, 32-bit data units are written / read at a time in the data RAM 23, while the CPU
Since the data width of 25 is 16 bits, the data RAM
Two accesses are required to write / read a 32-bit data unit to / from 23. For example CPU2
5 writes to the data RAM 23, the lower 16 bits (D0) of the 32-bit data (D0 to D31).
Through D15) via the gate 26 to the address N of the RAM 23
(D0 to D7 are stored) and address N + 1 (D
8 to D15 are stored simultaneously) and the remaining upper 16 bits (D16 to D31) are written to the bus controller 2
Address N + 2 (D16-
D23 is stored) and address N + 3 (D24-
D31 is stored).

In the case of 16-bit and 32-bit access, it is necessary to specify a plurality of addresses at the same time. Therefore, in the case of 16-bit access, two byte enable signals BL are used instead of the least significant bit LSB of the address.
E and BHE are the address N and the address N + 1, respectively.
It is designed to be assigned to multiple addresses simultaneously and individually. In the case of 32-bit access, the same method is used, instead of the lower 2 bits of the address, 4
One byte enable signal BE0-BE3 is assigned to address N-address N + 3, respectively. Hereinafter, when simply referred to as “the area of the address N”, the addresses N to
It is assumed that it refers to the space of address N + 3.

To the 32-bit data (D0 to D31), 4-bit parity bits (P0 to P3) are added, and the parity bits for the lower 16 bits (D0 to D15) are P0 and P1 2 bits, and the upper bit. Parity bits for 16 bits (D16 to D31) are P2, P
It is 2 bits of 3. That is, one parity bit is assigned to each byte of data. This parity bit (P0 to P3) is the parity R
It is stored in the AM 22. Writing to the parity RAM 22 is performed by so-called partial write (partial rewriting).

FIG. 7 is a diagram for explaining the concept of this partial rewriting. Here, from the CPU 25 having a data width of 16 bits to the lower 16 bits of the data RAM 23 having a data width of 32 bits.
The data D0 to D31 are written by accessing the upper 16 bits following the bit access, and at the same time, the parity for the data D0 to D31 is calculated and the area corresponding to the addresses N to N + 3 of the parity RAM 22 (specifically, Since the 32-bit bus is specified by BE0 to BE3 instead of the lower 2 bits of the address, the operation in the case of partial rewriting to the area specified by the address N) will be described.

The parity bits P0 to P3 are read from the area of the parity RAM 22 corresponding to the data D0 to D31.

The data D0 to D15 are stored in the data RAM 23.
This data D0 to D
The parity bit is calculated for 15 and the calculated parity bits P0 and P1 are converted to the parity RAM2 in the procedure.
P0 in the parity bits P0 to P3 read from
P1 replaced with the parity bit P0 after the replacement
~ P3 is written to the parity RAM 22.

The parity bits P0 to P3 are read from the area of the parity RAM 22 corresponding to the data D0 to D31.

The data D16 to D31 are stored in the data RAM 2
The data D16
The parity bits are calculated for D31 to D31, and the calculated parity bits P2 and P3 are used as the parity RA in the procedure.
P in the parity bits P0 to P3 read from M22
2 and P3, and the replaced parity bits P0 to P3 are written in the parity RAM 22.

FIG. 8 is a diagram showing a more specific conventional circuit for performing this partial rewriting, and FIG. 9 is an operation time chart thereof. In FIG. 8, 1 is a data section memory for storing data, 2 is a parity section memory for storing parity bits, 3 is control such as writing / reading with respect to the parity section memory 2, and a latch 5 described later. And selector 6
A parity control circuit that controls a and 6b, a parity generator that generates data parity, a latch 5 that temporarily holds the parity bit read from the parity unit memory 2, and selectors 6a and 6b.

In this conventional circuit, the data section memory 1
The operation in the case of writing the data D0 to D31 to the address N of will be described below with reference to FIG.

(1) First, the data D0 to D15 are written in the lower 16 bits of the area of the address N of the data memory 1. In this case, the read signal PRD from the parity control circuit 3 causes the data D0 to D from the parity unit memory 2 to be read.
The parity bits P0 to P3 corresponding to 31 are read out and stored in the latch 5. On the other hand, the parity generator 4 generates parity bits P0, P for the data D0-D15.
1 is generated. In response to the select signal from the parity control circuit 3, the selector 6a selects the parity bits P0 and P1 from the parity generator 4, and the selector 6b selects the parity bits P2 and P3 from the latch 5. Parity bits P0 to P3 from the selectors 6a and 6b
Is rewritten in the original area of the parity memory 2 by the write signal PWR from the parity control circuit 3.

(2) Next, the upper 16 of the area of address N
The data D16 to D31 are written in the bits. in this case,
Parity bits P0 to P3 corresponding to the data D0 to D31 are read from the parity section memory 2 by the read signal PRD from the parity control circuit 3 and stored in the latch 5. On the other hand, data D16 ...
Parity bits P2 and P3 for D31 are generated. By the select signal from the parity control circuit 3,
The selector 6a uses the parity bits P0, P from the latch 5
1, the selector 6b selects the parity bits P2 and P3 from the parity generator 4. These selectors 6
The parity bits P0 to P3 from a and 6b are rewritten in the original area of the parity memory 2 by the write signal PWR from the parity control circuit 3.

[0015]

As described above, in the case of a memory having a plurality of bits as stored data, the data stored in the memory cannot be rewritten on a bit-by-bit basis. However, there is no choice but to rewrite all bits at once. Therefore, to rewrite part of the data stored in the memory, first read all the bits of the data corresponding to the address to be rewritten in the memory from the memory, and then rewrite part of the data outside the memory (for example, on the latch). However, there is a problem that the operation speed becomes slower because of the two procedures of writing all the bits of the rewritten data in the memory again collectively.

Conventionally, as a method for solving this problem, for example, in the case of rewriting the above-mentioned parity bit, a method of omitting the writing procedure when the read parity bit and the newly calculated parity bit happen to coincide with each other is omitted. For example, it is known from JP-A-2-171945. However, with this method, when the bit width of the data increases,
Since the probability that the parity bits coincide with each other is extremely reduced, it is no longer an effective solution with the increase in the number of bits of memory elements in recent years.

The present invention has been made in view of such problems, and an object thereof is to enable partial rewriting of data at high speed.

[0018]

FIG. 1 is a diagram illustrating the principle of the present invention. In order to solve the above-mentioned problems, the present invention has one additional data per one data unit, and the data unit is divided and stored in consecutive addresses of the data unit memory, and the additional data is stored in the additional unit memory. A method for updating additional data in an additional unit memory according to an access to a data unit of a data unit memory in a stored memory system, wherein data is added from the additional unit memory by first address access to the data unit of the data unit memory. The additional data corresponding to the unit is read and held, the content of the additional data is updated outside the additional unit memory in subsequent successive address accesses to the data unit, and the updated additional data is updated at the final address access to the data unit. Memory control method for writing to the original address of the additional memory It is provided.

In the above memory control method, when address access to a data unit is discontinuous or interrupted midway, the additional data held outside the additional unit memory is written to the original address of the additional unit memory. May be.

In the present invention, as another form,
A data unit memory that stores the data unit by dividing it into a plurality of consecutive accesses, an additional unit memory that stores additional data corresponding to the data unit, and an additional unit that generates partial additional data for the divided data unit. Data generating means, reading means for reading additional data corresponding to the data unit from the additional unit memory at the time of first address access to the data unit, latch for temporarily holding the additional data read by the reading means, and storage in the latch Update means for updating the additional data to be generated with the partial additional data from the additional data generating means, and a writing means for writing the additional data of the latch to the original address of the additional portion memory at the time of the last address access to the data unit. A memory control circuit is provided.

In the above-mentioned memory control circuit, an address storage means for storing an address of an additional memory for storing additional data for a data unit, and a first for detecting whether or not an address access address for a data unit is continuous. And second detecting means for detecting that the address access to the data unit is interrupted midway, and the first or second detecting means determines that the address access is discontinuous or interrupted. At this time, the additional data of the latch may be rewritten to the address stored in the access storage means of the additional memory.

[0022]

For example, as illustrated in FIG. 1, in the case of sequential access to consecutive addresses of the data section memory, the additional section memory is continuously accessed twice. During the first half access, the additional data is read from the additional memory and the contents are partially updated and held, and during the second access, the additional data is partially updated and the updated additional data is collected in the additional memory. If the data is written by writing, it is possible to shorten the access time by partial writing to the additional memory.

If the addresses in the latter half access are not continuous, or if the access is interrupted after the first half access, the externally held additional data is returned to the original address of the additional portion memory and the partial writing is promptly performed. Complete.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a memory control circuit as an embodiment of the present invention. Although this embodiment will be described in the case where the number of parity bits is 4 for simplification of description, it can be realized by a similar method even if the number of parity bits is increased.

In FIG. 2, 1 is 32 per address.
A data unit memory that stores bit data, 2 a parity unit memory that stores 4-bit parity bits P0 to P3, 3 write / read control of the parity memory 2, and selectors 6a, 6b and 9 latches 5 and 7. A parity control circuit for controlling the parity and the like, 4 a parity generator for generating a parity bit (2 bits) from data (16 bits), 5
Is a latch for temporarily storing the parity bit read from the parity memory 2 and the parity bit generated by the parity generator 4, and 6a and 6b are selectors for partially updating the parity bit.

Reference numeral 7 is a latch for temporarily holding an address, and 8 is for detecting whether or not the current address from the common bus and the previous address held in the latch 7 match. Of the exclusive OR circuit for detecting whether or not all bits in both addresses except byte enable match, and outputs a match signal to the parity control circuit 3. Reference numeral 9 is a selector for switching the address input to the parity unit memory 2 between the current address from the common bus and the previous address from the latch 7. Further, both the host and the common bus have a 32-bit width, but the CPU and the protocol processor in the communication card have a 16-bit width, and are therefore connected through the bus width conversion circuit of FIG.

Since the address input to the selector 9 (thus, the address input to the parity unit memory 2) does not include byte enable, two consecutive addresses N from the CPU to the data unit memory 1 (in the 16-bit bus, Address N + 1 is simultaneously accessed with N), N +
For 2 (similar access to N + 3 as well), the address input to the parity memory 2 becomes one common address. Data D0 to D31 are stored in the parity unit memory 2.
Parity bits P0 to P3 for the are stored. That is, one parity bit is assigned to each byte of data. The parity generation record 4 generates parity bits P0 and P1 for the upper 16 bits (D0 to D15) of the data D0 to D31 and parity bits P2 and P3 for the lower 16 bits (D16 to D31).
Generate

The operation of the circuit of this embodiment will be described below with reference to the time charts of FIGS. Here, FIG. 3 is a time chart in the case of continuous access in which the addresses for accessing the data section memory 1 from the CPU are continuous, and FIG. 4 is a time chart in the case where the addresses for accessing the data section memory 1 from the CPU are discontinuous. Chart, CPU in Figure 5
6 is a time chart in the case where the access to the data unit memory 1 is interrupted.

First, the operation in the case of continuous access from the CPU will be described with reference to FIG. (1) First, the addresses N to N + 1 of the data section memory 1
The data D0 to D15 are written over. This address N is temporarily held in the latch 7. In this case, the selector 9 selects the current address N from the common bus according to the instruction from the parity control circuit 3. Parity control circuit 3
Parity bits P0 to P0 corresponding to the data D0 to D31 from the parity memory 2 by the read signal PRD from
P3 is read. On the other hand, the parity generator 4 generates parity bits P0 and P1 for the data D0 to D15. When the parity bit generation of the parity generator 4 is completed, the selector 6a selects the parity bits P0 and P1 from the parity generator 4 by the select signal from the parity control circuit 3, and the selector 6b outputs the parity bit from the parity unit memory 2. The parity bits P2 and P3 are selected. Therefore, in the parity bits P0 to P3 input to the latch 5, the parity bits P0 and P1 in the parity bits P0 to P3 are generated by the parity generator 4, and the parity bits P2 and P3 are the parity unit memory 2.
Stored in the latch 5, and this is input to and held in the latch 5.

(2) Next, data D16 to D31 are written from addresses N + 2 to N + 3. In this case, the previous address N held in the latch 7 and the current address N + 2 from the common bus match because the lower 2 bits of the address are represented by the byte enables BE0 to BE3, and the exclusive OR circuit 8 The parity control circuit 3 determines that consecutive addresses have been accessed from the CPU based on the coincidence signal. On the other hand, the parity generator 4 generates parity bits P2 and P3 for the data D16 to D31, and the selector 6b selects the parity bits P2 and P3 from the parity generator 4. Therefore, latch 5
The parity bits P0 to P3 input to the parity bit P0 to P3 are the ones generated previously by the parity generator 4 in the parity bits P0 to P3, and the parity bits P2 and P3 are generated at the parity generation record 4 this time. And the latch 5 holds it. The parity bits P0 to P3 of the latch 5 are rewritten in the original area of the parity memory 2 by the write signal PWR from the parity control circuit 3.

As described above, in the embodiment circuit, the address at the time of the immediately preceding memory access is temporarily stored in the latch 7, and the exclusive OR circuit 8 stores the address of the latch 7 and the address of the current memory access. Are compared with each other, it is determined that the content of the latch 5 temporarily storing the parity bit of the immediately preceding memory access matches the parity bit to be read from the parity unit memory 2 in the current memory access, and the data is written in the latch 5. Value is selector 6a, 6b
By selecting with, the latter half data D16 to D3
By omitting the procedure of reading the parity bits P0 to P3 from the parity unit memory 2 to the latch 5 for 1, the partial rewriting is performed at high speed. By thus combining the two memory accesses in the conventional example into one, rewriting can be performed at twice the speed as compared with the conventional example shown in FIG.

Next, the operation when addresses are not consecutive when accessed from the CPU will be described below with reference to FIG. When the memory access address in the first half process (1) is N, while the memory access address in the second half process (2) is N + α, the addresses match as a result of comparison in the exclusive OR circuit 8. It is determined not to. In this case, according to an instruction from the parity control circuit 3, the selector 9 selects the previous address N stored in the latch 7 and supplies it to the parity unit memory 2. A write cycle is generated by the parity control circuit 3, the content of the latch 5 is written to this address N of the parity memory 2, and the partial rewriting is completed. After that, the latch 7 holds the current address N + α and processes subsequent accesses.

Next, the operation when there is no access from the bus master even after a fixed time has passed will be described below with reference to FIG. When there is no next access from the bus master even after a certain time elapses after the access to the address N, the elapse of the certain time is detected by the timeout of the timer built in the parity control circuit 3 in order to complete the partial rewriting. . Then, according to an instruction from the parity control circuit 3, the selector 9 selects the previous address N stored in the latch 7 and supplies it to the parity unit memory 2. The write cycle is generated by the parity control circuit 3, and the latch 5
The parity bit of is written in the address N of the parity memory 2 to complete the partial rewriting.

In the case of the operations shown in FIGS. 4 and 5, since the bus cycle is extended, the access from the common bus is waited by the ready signal READY output from the parity control circuit 3.

Various modifications are possible in implementing the present invention. For example, in the above-described embodiment, the 16-bit bus master stores the 16-bit data in the data unit memory 1, and the parity bit is also accessed twice as the data unit memory 1 is accessed twice. However, of course, the present invention is not limited to this. For example, when the common bus is 64 bits, 16 bits are stored in the data section memory 1 from the 16-bit bus master. The parity bit may be accessed four times in association with the four accesses to 1. In this case, the parity bit is read from the parity unit memory 2 by the first address access and held in the latch, and the second time,
At the time of the third address access, the contents of the parity bit are updated on the latch and the last (fourth) address
At the time of access, the contents of the latch (updated parity bit) are returned to the parity unit memory 2.

[0036]

As described above, according to the present invention, the address of the immediately preceding memory access and the data for partial rewriting can be held, and the read procedure accompanying partial rewriting can be omitted, so that partial rewriting can be performed at high speed. It can be carried out.

In particular, in the case of sequentially accessing addresses such as DMA transfer, rewriting can be performed at the same speed as a normal all-word writing. The present invention has a remarkable effect in a system in which partial rewriting is frequently performed, such as an access from a bus master having a bus width different from that of the data memory.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a memory control circuit as one embodiment of the present invention.

FIG. 3 is a time chart in the case of continuous access in which addresses for accessing the data section memory 1 in the example circuit are continuous.

FIG. 4 is a time chart when the addresses for accessing the data memory 1 in the embodiment circuit are discontinuous.

FIG. 5 is a time chart when the access to the data unit memory 1 in the circuit of the embodiment is interrupted.

FIG. 6 is a diagram showing a configuration example of a communication card.

FIG. 7 is a diagram for explaining the concept of partial rewriting.

FIG. 8 is a block diagram showing a conventional memory control circuit that performs partial rewriting.

FIG. 9 is a time chart of a conventional circuit.

FIG. 10 is a block diagram showing a bus width conversion circuit.

[Explanation of symbols]

 1 data section memory 2 parity section memory 3 parity control circuit 4 parity generator 5 parity bit holding latch 6a, 6b parity bit selecting selector 7 address holding latch 8 exclusive OR circuit 9 address selecting selector 20 Communication Card 21 Bus Controller 22 Parity RAM (Random Access Memory) 23 Data RAM (Random Access Memory) 24 Protocol Controller 25 CPU (Central Processing Unit) 26, 27 Gate 30 Host Computer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Keiko Yuki, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, within Fujitsu Limited

Claims (4)

[Claims] 1. A memory system having one additional data per one data unit, the data unit being divided and stored in consecutive addresses of a data unit memory, and the additional data being stored in the additional unit memory. A method of updating additional data of the additional unit memory in accordance with an access to a data unit of the data unit memory, wherein the additional unit memory is changed from the additional unit memory to the data unit by first address access to the data unit of the data unit memory. The corresponding additional data is read and held, the contents of the additional data are updated outside the additional unit memory in subsequent successive address accesses to the data unit, and the updated additional data is accessed at the final address access to the data unit. A memory control method in which is written to the original address of the additional memory. 2. When the address access to the data unit is discontinuous or interrupted on the way, the additional data held outside the additional unit memory is written to the original address of the additional unit memory. Item 2. The memory control method according to Item 1. 3. A data unit memory for storing a data unit divided into a plurality of continuous accesses, an additional unit memory for storing additional data corresponding to the data unit, and divided data obtained by dividing the data unit. Additional data generating means for generating partial additional data, reading means for reading additional data corresponding to the data unit from the additional memory at the first address access to the data unit, and additional data read by the reading means. A latch that is temporarily held, an updating unit that updates the additional data stored in the latch with the partial additional data from the additional data generation unit, and additional data of the latch at the last address access to the data unit. And a writing means for writing to the original address of the additional unit memory. 4. An address storage means for storing an address of said additional unit memory for storing additional data for said data unit, and a first detection for detecting whether or not addresses of address access for said data unit are continuous. Means and second detecting means for detecting that the address access to the data unit is interrupted on the way, and the first or second detecting means determines that the address access is discontinuous or interrupted. 4. The memory control circuit according to claim 3, wherein the additional data of the latch is rewritten to the address stored in the access storage means of the additional unit memory when the latching is performed.