GB2177253A

GB2177253A - Electrical interconnection arrangement

Info

Publication number: GB2177253A
Application number: GB08516441A
Authority: GB
Inventors: Martin Paul Mobberley; Maurice Lionel Apthorp; Maurice Clifford Heard
Original assignee: General Electric Co PLC
Current assignee: General Electric Co PLC
Priority date: 1985-06-28
Filing date: 1985-06-28
Publication date: 1987-01-14
Also published as: GB2177253B; GB8516441D0

Abstract

An electrical interconnection arrangement enables a temporary connection to be made to a very small semiconductor chip for testing purposes without damaging its delicate terminal pads. A thin flexible transparent substrate 3 of electrically insulating material which carries a pattern of conductors is used to link the semiconductor chip 1 to a relatively robust printed circuit board 9. The ends of the conductors which contact the pads 2 of the chips are provided with bumps 14 which project into the recesses within which the terminal pads are often located. The application of pressure e.g. through a suction aperture 16 holds the flexible substrate in contact both with the chip and the printed circuit board. <IMAGE>

Description

SPECIFICATION Electrical interconnection arangement This invention relates to an electrical interconnection arrangement which is suitable for making temporary connection with a very small electrical circuit component without causing damage to it. Electrical circuit components are commonly formed in very small pieces of semiconductor material and access to such a circuit is generally via localised pads of conductive material which are extremely thin and delicate.Permananent electrical connections can be made to the localised pads by bonding the ends of a conductive wire to each, but before permanently connecting the electrical circuit component into a larger system or circuit it is very desirable to first test it to ensure that it is operating correctly and is not defective This testing can be achieved by bringing elongate needle-like probes into contact with respective pads so as to permit connection to suitable electrical test equipment, but the positioning of the probes is very critical and the ends of the probes can cut into the pad surfaces and/or seriously distort them so that although the circuit component on test is found to be electrically correct it may be so damaged thereby that it is no longer suitable for use for the purpose for which it is made.

This difficulty is a very real one as the dimensions of the pads can be so very small, and the nature of the pads is invariably extremely fragile.

The present invention seeks to provide an improved electrical interconnection arrangement.

According to this invention an electrical interconnection arrangement includes a plurality of conductors to which a semiconductor device having localised terminal regions is to be temporarily connected; means adjacent to said plurality of conductors for accepting and positioning said semiconductor device; and a planar electrically insulating substrate carrying a pattern of electrical conductors upon one surface thereof and which co-operates with said plurality of conductors, and with said terminal regions whereby said conductive pattern serves to link the localised terminal regions with predetermined regions of said plurality of conductors.

Preferably the electrically insulating substrate is flexible so that the application of pressure forms good electrical contacts with said terminal regions and with said plurality of conductors. Conveniently, the electrical insulating substrate is transparent so that the pattern of electrical conductors which it carries can be seen from its rear surface to facilitate its alignement with the semiconductor device.

The invention is intended to facilitate the electrical testing of unencapsulated semiconductor chips and such chips can be very small so that their localised terminal regions will be very small indeed requiring very accurate positioning of the substrate.

The flexible substrate preferably takes the form of a diaphragm which in use is held in contact with the semiconductor chip by means of a suction effect or by means of a pressure pad applied to the reverse surface of the diaphragm. As the localised terminal regions can take the form of pads which are recessed into the upper surface of the semiconductor chip, it is desirable for the ends of the pattern of electrical conductors carried by the diaphragm to be provided with a raised portion or bump which is positioned so as to penetrate into the recess in order to ensure a good and reliable electrical contact. The bumps can be formed by a sputtering process, or alternatively and preferably by intaglio printing in which the profile of a raised region of printed conductive ink is determined by the shape of a corresponding recess in a printing plate.In this context, the ink may be applied as a fluid or paste and embraces any suitable settable material-it is termed an ink as it is applied by a printing process customarily used for precision printing purposes in the literary and artistic fields.

The invention is further described by way of example with reference to the accompanying drawing in which: Figure 1 shows a plan view of an electrical interconnection arrangement, and Figure 2 is an enlarged sectional view.

Referring to the drawing there is shown therein a small semiconductor chip 1 which is of the kind which is fabricated in large numbers on a large area thin slice of silicon which is subsequently divided up into very many small individual electrical circuits mounted on its own piece of silicon. Such electrical circuits are generally termed chips and the upper surface often carries a very large number of individual semiconductor devices such as transistors and logic gates which are interconnected by a complex pattern of conductive leads or tracks which terminate in this example in fourteen separate pads 2 located around the periphery of the chip.These pads 2 consist of localised regions of a very thin layer of electrically conductive material such as aluminium and it is to these pads that permanent electrical connection is made when the chip is incorporated into the electrical system in which it is to operate. A number of well known tech niques exist for mounting the semiconductor chip and for making the permanent electrical connections to the pads but it has proved difficult to make a temporary electrical connection to the pads for the purpose of facilitating electrical testing of the chip. It is very desirable and often necessary to thoroughly electri cally test a chip to ensure that its circuit functions are correct since it is time consuming and expensive to subsequently remove and re place a chip after it has been permanently inserted into its circuit.

In order to permit reliable and temporary electrical connection to be made to these localised pads, a flexible substrate 3 is provided upon which very thin electrically conductive leads 4 are carried. The substrate 3 is of a thin transparent electrically insulating plastics material and the conductive tracks 4 could be formed by selectively etching a continuous electric foil carried on one of its outer surf aces. Each track 4 as shown in Figure 1, consists of three distinct portions; an extremely fine narrow portion 5 which makes contact with a pad 2, a contact area 7 which is of sufficiently large shape as to make contact with co-operating contact pads 8 formed on a printed circuit board-like circuit 9 and an intermediate wider portion 6 which links the end portion 5 to the area 7.

The printed circuit board 9 is a relatively large robust rigid plate mounted on a support 10 and which has a central aperture 11 within which the chip 1 is located. The printed circuit board 9 can interface with conventional test equipment and other circuits in the usual manner without difficulty by means of conductive tracks 13 which it bears and the purpose of the flexible substrate 3 is to provide a special temporary electrical interconnection between the terminal pads 12 of the printed circuit board 9 and the localised pads 2 of the chip 1.

It will be seen from Figure 2 that the portion 5 of the leads 4 are provided with a bump 14 which serves to penetrate into a recess within which the pad 2 is located on the chip 1. Because of the way in which semiconductor devices are processed, it frequently happens that the contact pads are slightly recessed below the upper surface of the chip making contact relatively difficult unless a very narrow shaped rigid probe is used in accordance with the previously known arrangements. In the present instance, it is the small bump 14 which locates within the recess and provides good electrical contact when the flexible substrate 3 is brought firmly into contact with the chip by urging it in the direction of the arrows 15.

This firm contact can be achieved in a number of ways, one of which comprises applying a suction to the apertures 16 (only one of which is shown) in the supporting plate 10 around the chip 1 so as to draw downwardly the flexible substrate 3. Suitable apertures could be placed in the printed circuit board 9 in the vicinity of the pads 12 to ensure electrical contact between the two sets of pads 7 and 12. Alternatively, instead of using a suction arrangement, a small block can be placed immediately over the region of the substrate 3 above the chip and suitable pressure applied, it being relatively simple to squeeze the outer periphery of the substrate 3 between two plates one of which constitutes the printed circuit board 9 so as to ensure good electrical contact at those regions.

In practice once the flexible substrate 3 has been placed over the printed circuit board 9 and clamped thereto, the chip 1 will be moved by means of a vernier table (not shown) which is capable of providing fine and precise movement in two orthogonal directions until the end portions 5 of the leads 4 are accurately aligned with the pads 2. This can be readily verified since the substrate 3 is transparent thereby enabling an operator to see when the correct position has been achieved.

The bumps 14 on the ends of the leads 4 can be formed by any convenient method such as sputtering on to the etched conductive tracks. Such a process however, is difficult to control and expensive to implement and it is therefore preferred to form all of the conductive paths on the flexible substrate 3 by means of intaglio printing. In intaglio printing, the ink carrying areas of a printing plate are recessed hollows below its surface so that the thickness of the layer of ink transferred to the substrate is according to the depths of the hollows. The printing plate can take the form of a cylindrical surface or a flat surface and in this context the term ink embraces any settable fluid having predetermined electrically conductive properties. By suitably forming the hollows in the printing plate a very high degree of accuracy and precision can be achieved both as to the width of the conductive portions 5 and as to the height and profile of the bumps 10 thereby enabling a very reliable interconnection to be achieved which causes no damage to the chip 1.

Claims

1. An electrical interconnection arrangement including a plurality of conductors to which a semiconductor device having localised terminal regions is to be temporarily connected; means adjacent to said plurality of conductors for accepting and positioning said semiconductor device; and a planar electrically insulating substrate carrying a pattern of electrical conductors upon one surface thereof and which cooperates with said plurality of conductors and with said terminal regions whereby said conductive pattern serves to link the localised terminal regions with predetermined regions of said plurality of conductors.

2. An arrangement as claimed in claim 1 and wherein the electrically insulating substrate is flexible.

3. An arrangement as claimed in claim 1 and wherein the electrically insulating substrate is transparent.

4. An arrangement as claimed in any of the preceding claims and wherein the conductors carried by the electrically insulating substrate are provided with bumps where they co-oper ate with the localised terminal regions of the semiconductor device.

5. An arrangement as claimed in any of the preceding claims and wherein the pattern of electrical conductors carried by the planar electrically insulating substrate is formed thereon by intaglio printing.

6. An arrangement as claimed in any of the preceding claims and wherein the semiconductor device is mounted so as to be movable in two orthogonal directions with respect to the said plurality of conductors.

7. An electrical interconnection arrangement substantially as illustrated in and described with reference to the accompanying drawings.