JPH09159694A - Lsi test probe - Google Patents

Abstract

PROBLEM TO BE SOLVED: To produce an LSI test probe easily at low cost by forming a wiring pattern of transparent conductor on the surface of a laminate of a glass substrate and a transparent anisotropic conductive sheet. SOLUTION: A wiring pattern 2 of indium tin oxide is formed on the lower surface of a glass substrate 1 by photolithoqraphy and a transparent anisotropic conductive sheet (ACF) is applied thereon. The wiring pattern 2 comprises a probe part 22 facing the I/O terminal 4 of an LSI chip 5 to be measured, an electrode part 21 to be connected with a tester, and a lead-out part 23 connecting them. The LSI test chip is aligned by superposing a probe over the chip 5 without touching, aligning the I/O terminal 4 and the probe part 22, and then superposing the chip 5 and ACF 3 tightly. In this regard, the probe part 22 and the I/O terminal 4 of chip 5 are connected electrically through the vertical conductivity of the ACF 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LS used when inspecting a semiconductor integrated circuit device (referred to as "LSI").
Regarding the I test probe device, L which is particularly suitable for testing an LSI in a wafer state or a bare chip state
The present invention relates to an SI test probe device.

[0002]

2. Description of the Related Art Recently, in order to mount an LSI at a high density, the LSI is directly mounted on an electronic circuit board without putting it in a case.
The bare chip mounting method for mounting an SI chip has been widely adopted.

However, since the bare chips are tested in a wafer state and then cut into individual chips and supplied, the quality after cutting is not guaranteed (even if the bare chips are judged to be non-defective by a wafer test by a wafer prober, the bare chips are always non-defective. It is not always possible to maintain the state and there is a problem in terms of reliability). Therefore, the bare chip test method has become a technical issue.

The LSI is usually enclosed in a case made of molding resin, ceramics or the like, and its input / output terminals are connected to the input / output pins (lead pins) of the case.

Since an LSI test (test after sealing in a package) may be performed on this input / output pin, L
It can be tested without damaging the SI chip.

However, in the case of a bare chip, since it is necessary to apply a test probe to the LSI chip body, the LSI chip may be damaged by the test probe. This is the same when testing the LSI in a wafer state (wafer test).

That is, since the conventional test probe has a needle-like shape with a sharp tip, there is a possibility that the metal film of the input / output portion (pad) of the LSI chip may be destroyed, resulting in irreparable damage. It was

As a test probe device intended to avoid damaging an object to be measured such as a printed circuit board, for example, Japanese Patent Laid-Open No. 2-59676 discloses a printed circuit board on which electronic parts are mounted and a rod-shaped metal. An anisotropic conductive sheet having elasticity is interposed between the probe and the probe.
A probe device for a board tester has been proposed in which a probe is brought into contact with a predetermined position on a printed board via an anisotropic conductive sheet. That is, in the publication, an anisotropic anisotropic conductive sheet (ACF) having elasticity is interposed between a test probe having a sharp protrusion and an object to be measured to avoid damaging the object to be measured. It is what

FIGS. 3A and 3B are side views for explaining the configuration of the test probe described in the above publication. As shown in FIG. 3A, the soldering portion 33 of the chip component 36 or the like on the printed circuit board 31 and the probe 3
4, an anisotropic conductive sheet 35 having conductivity in the direction of the printed circuit board 31 and the probe 34 is arranged between them and the probe 34 in FIG. 3B. In the figure, a state in which is applied is shown, and an electrical connection can be obtained between the printed board 31 and the probe 34.
Since the anisotropic conductive sheet 35 is made of elastic rubber or resin, no abnormal force is applied to the printed board 31 and it is not damaged.

[0010]

However, the first problem with this conventional test lobe device is that such a test probe is difficult and very expensive to manufacture. The reason will be described in detail below.

That is, the number of input / output terminals (the number of pins) of the LSI is increasing with the high integration, and it is currently 100.
Some are close to zero. On the other hand, the pitch and diameter of input / output terminals have been reduced, and the pitch is 100 μm and the diameter is 50 μm.
It has reached about m.

Nearly 1000 test probes are 100 μ
It is very difficult to fabricate a test probe device by arranging it accurately with a pitch, and as a result, the test probe device is very expensive due to a long production period and a low yield. .

The second problem of the conventional test probe apparatus is that it is difficult to align the individual probes with the input / output terminals of the LSI, and it takes a lot of time.

That is, the alignment is performed while observing the input / output terminals of the LSI chip and the tip of the test probe with a microscope. However, since nearly 1000 test probes are concentrated, the input / output terminals of the LSI chip are hidden. Is.

And the third of the conventional test probe devices
However, such a test probe device cannot cope with high integration of LSI.

The reason is that the test probe needs mechanical strength in order to make contact with the input / output terminals. For this reason, miniaturization cannot be performed, and it is impossible to cope with an increase in the number of input / output terminals of the LSI and a reduction in pitch. Also, from the point of alignment described as the above-mentioned second problem, it is impossible to deal with high integration.

The object of the present invention is to solve the above-mentioned problems of the prior art, achieve a cost reduction without damaging the surface of the LSI chip, facilitate alignment, and support high integration. To provide a simple test probe device.

[0018]

To achieve the above object, the present invention provides a test probe device comprising a glass substrate and a transparent anisotropically conductive sheet bonded together, wherein the anisotropic conductivity of the glass substrate is used. Provided is an LSI test probe device characterized in that a wiring pattern made of a transparent conductor is provided on a surface to which a conductive sheet is attached.

[0019]

In the present invention, the portion which comes into contact with the object to be measured is an anisotropic conductive sheet (ACF), and therefore the object to be measured is not damaged.

Further, according to the present invention, the test probe is formed by a wiring pattern made of a transparent conductor. Since it is manufactured by forming a thin film layer of a transparent conductor on a glass substrate and then patterning it by photolithography technology, it is easy to form a high-density wiring pattern with high accuracy and at a low cost. In addition, it is possible to realize high integration.

Further, according to the present invention, since the probe device is composed of the glass substrate, the transparent conductor and the transparent anisotropic conductive sheet (ACF), the LSI chip can be easily seen at the time of alignment and the alignment is easy. It has the advantage that

[0022]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a test probe apparatus according to an embodiment of the present invention, FIG. 1 (A) is a sectional view, and FIG. 1 (B) is a top view.

As shown in FIG. 1, in the test probe device according to this embodiment, a wiring pattern 2 made of ITO (indium tin oxide) is formed on the lower surface of a glass substrate 1.

The wiring pattern 2 is formed by the following method. First, a uniform ITO thin film is formed on one surface of the glass substrate 1, and a photoresist is applied on the entire surface of the ITO thin film and dried. This is irradiated with ultraviolet light through a glass mask on which a desired pattern is formed, and then developed. Then, since the photoresist remains only in a predetermined pattern portion, the exposed ITO is etched and the last remaining photoresist is removed. This pattern forming method is called photolithography technology.
Is used for pattern formation.

After the wiring pattern made of ITO is formed in this manner, a transparent anisotropic conductive sheet (A
CF) 3 is attached. The ACF 3 has conductivity only in the vertical direction in FIG.

As shown in FIG. 1B, the wiring pattern 2 has a probe portion 22 facing the input / output terminals of the LSI chip to be measured and an electrode portion 21 for connecting to a tester.
And a lead-out portion 23 connecting the two.

Next, the alignment of the test probe device and the LSI test chip according to this embodiment will be specifically described with reference to FIGS. 1 and 2.

At the time of the test, first, the probe device is placed on the LSI chip 5 so that the probe device does not come into contact with the chip 5, and the input / output terminal 4 and the probe portion 22 are observed from above with a microscope.
Is aligned with When the positions are aligned, as shown in FIG. 2, the LSI chip 5 and the ACF 3 are superposed so as to be in close contact with each other. At that time, the probe unit 2 of the test probe device
2 and the input / output terminal 4 of the LSI chip 5 are electrically connected by the vertical conductivity of the ACF 3.

The bare-chip test probe apparatus according to this embodiment is easy and inexpensive to manufacture because the wiring including the probe portion is formed by the photolithography technique. Further, in this embodiment, since the same technique as the pattern formation of the LSI is used, it is possible to form a fine pattern, and it is possible to cope with high integration. Further, since the glass substrate 1, the ITO 2 and the ACF 3 are all transparent, the alignment is easy and can be done in a short time.

[0031]

As described above, according to the present invention,
Since the wiring pattern including the probe portion is formed by the photolithography technique, the LSI test probe device can be easily manufactured at low cost.

Further, according to the present invention, a glass substrate, IT
Since O and ACF are all transparent materials, there is an effect that the alignment is easy and the inspection time can be shortened.

Further, according to the present invention, by using the same photolithography technique as that of the LSI for forming the wiring pattern, it is possible to cope with high integration, and it is possible to increase the number of pins and the pitch with the high integration. It has the effect of being able to respond.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. (A) is a sectional view. (B) is a plan view.

FIG. 2 is a cross-sectional view for explaining a function and effect of one embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a conventional test probe device.

[Explanation of symbols]

 1 glass substrate 2 wiring pattern 3 ACF 4 input / output terminal 5 LSI chip 21 electrode part 22 probe part 23 lead-out part

Claims (3)

[Claims] 1. A test probe apparatus comprising a glass substrate and a transparent anisotropic conductive sheet attached to each other, wherein a wiring made of a transparent conductor is provided on a surface of the glass substrate on which the anisotropic conductive sheet is attached. An LSI test probe device characterized in that a pattern is provided. 2. A wiring pattern made of the transparent conductor,
A probe section facing an input / output terminal of an LSI chip to be measured, an electrode section for electrically connecting to a test apparatus, and a lead section connecting the probe section and the electrode section. Item 1. The LSI test probe device according to Item 1. 3. The LSI test probe device according to claim 1, wherein the wiring pattern of the transparent conductor is formed by a photolithography process.