GB2244864A - Semiconductor device electrode pads - Google Patents
Semiconductor device electrode pads Download PDFInfo
- Publication number
- GB2244864A GB2244864A GB9111855A GB9111855A GB2244864A GB 2244864 A GB2244864 A GB 2244864A GB 9111855 A GB9111855 A GB 9111855A GB 9111855 A GB9111855 A GB 9111855A GB 2244864 A GB2244864 A GB 2244864A
- Authority
- GB
- United Kingdom
- Prior art keywords
- semiconductor device
- electrode pads
- pads
- probe
- circuit layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The present invention provides a semiconductor device formed in a semiconductor chip (20), comprising a circuit layer, a plurality of electrode pads (22) formed on either the upper surface or lower surface of the semiconductor chip and connected to the circuit layer, and a plurality of probe pads (24) formed in combination with and connected to the electrode pads, respectively. In inspecting the semiconductor device, probes (25) of an automatic wafer probe are brought into contact with the probe pads, respectively, so that the circuit layer underlying the electrode pads are not strained or fissured to make the semiconductor device faulty, and the surfaces of the electrode pads to be connected to leads (27) of a lead frame or terminals of a circuit are not damaged. Thus, a normal semiconductor device is not damaged in the inspection process, mounting a faulty semiconductor device on a lead frame is obviated, and the imperfect connection of the semiconductor device to the leads of the lead frame attributable to damages formed in the surfaces of the electrode pads with the probes can be prevented. <IMAGE>
Description
SEMICONDUCTOR DEVICE
The present invention relates to a semiconductor device provided with special probe pads for inspection.
In manufacturing a semiconductor device, in general, a circuit layer is formed on a semiconductor crystal substrate by a plurality of processes including an oxide film forming process, an impurity diffusing process, an ion implanting process and a thin film forming process, such as a CVD (chemical vapor deposition) process, a vapor deposition process and a sputtering process, and then, an insulating layer, a protective layer and electrode pads are formed on the circuit layer.
The semiconductor device is mounted on a lead frame and the electrode pads of the same are connected to the leads of a lead frame by wire bonding.
Referring to Fig. 7, a generally known conventional semiconductor device 1 comprises a semiconductor crystal substrate, a circuit layer formed on the semiconductor crystal substrate by a plurality of processes, a protective layer 2 covering the circuit layer, and a plurality of electrode pads 3. In forming the electrode pads 3, portions of the protective layer 2 corresponding to the electrode pads 3 are removed.
The semiconductor device 1 is mounted on a lead frame in one of mounting configurations shown in Figs. 8, 9 and 10.
In the mounting configuration shown in Fig. 8, the electrode pads 3 of the semiconductor device 1 are connected to leads 5, i.e., external electrodes, by wires 6. This connecting method is called a wire bonding method. In the mounting configuration shown in Fig. 9, the electrodes 3 of the semiconductor device 1 are connected to the leads 7 of a tape carrier by using bumps 8. This connecting method is called a TAB (tape automated bonding) method. In the mounting configuration shown in Fig.
10, an inner lead frame 11 and an outer lead frame 12 are attached adhesive lv to the opposite sides of a double coated z adhesive tape 10 of polyimide or the like, the semiconductor device 1 is placed in a device hole 13 formed in the double coated adhesive tape 10, and then the electrode pads 3 of the semiconductor device 1 are connected to the leads of the inner lead frame 11 by using bumps 14.
The semiconductor device 1 must be inspected before mounting the same on a lead frame in mounting the semiconductor device 1 on a lead frame in any one of the foregoing mounting configurations to see if the electric characteristics of the semiconductor device 1 are normal.
Conventionally, an automatic wafer prober, i.e., an inspection instrument, is used for inspecting the semiconductor device 1, in which a plurality of probes of the automatic wafer prober are brought into contact with the electrode pads 3 of the semiconductor device 1 to supply current to the circuit of the semiconductor device 1.
If the pressures of the probes of the automatic wafer prober to be applied to the electrode pads 3 are not adjusted properly or if the semiconductor device 1 is inclined to the probes of the automatic wafer prober, some of the probes are pressed against the corresponding elec trode pads 3 at an extraordinarily high pressure to fissure the circuit layer under the excessively pressed electrode pads 3. Conseguently, the semiconductor device 1 is damaged by inspection using the automatic wafer prober and the faulty semiconductor device may be mounted on a lead frame.
As shown in Fig. 11, in a conventional semiconductor device, electrode pads 3 are surrounded by a protective layer 2, ad the pe ripheries of the electrode pads 3 are covered with the stepped edges 2a of the protective layer 2. In Fig. 11, indicated at 15 is a substrate, at 16 is a circuit layer, at 17 is an isolating layer, at 18 are probes and at 19 is an insulating layer. If the probe 18 is brought into contact with the periphery of the electrode pad 3 at a high pressure, the stepped edge 2a of the protective layer 2 is pressed laterally by the probe 18 to fissure the insulating layer 19 formed under the electrode pad 3, so that the semiconductor device 1 becomes faulty.
Furthermore, the probes form dents in the surface of the electrode pads 3 in inspecting the conventional semiconductor device by the automatic wafer prober, and the dents are liable to cause incomplete electrical connection of the electrode pads 3 to the leads in connecting the electrode pads 3 to the leads by wire bonding.
Still further, in mounting the semiconductor device on a lead frame by the TAB method, the electrode pads are liable to be connected electrically imperfectly to the leads of the lead frame due to the difference in height between the bumps.
The present invention has been made to solve the foregoing problems and it is therefore an object of the present invention to provide a semiconductor device constructed so that its layers formed under its electrode pads may not be fissured in inspecting the semiconductor device with probes to spoil the semiconductor device before mounting the same on a lead frame.
In one aspect of the present invention, a semiconductor device formed in a semiconductor chip comprises a circuit layer, and a plural ity of electrode pads formed on either one surface or the other of the semiconductor chip and connected to the circuit layer. The semiconduc- tor device is characterized in that probe pads are formed near and in comnination with the electrode pads, respectively, and are connected to the circuit layer connected to the corresponding electrode pads.
In another aspect of the present invention, a semiconductor device formed in a semiconductor chip comprises a circuit layer, and a plurality of electrode pads formed on either one surface or the other of the semiconductor chip and connected to the circuit layer. The semiconductor device is characterized in that probe pads are formed on the upper surface of the semiconductor chip in combination with the electrode pads formed on the lower surface of the semiconductor chip, respectively, probe pads are formed on the lower surface of the semiconductor chip in combination with the electrode pads formed on the upper surface of the semiconductor chip, respectively, and the probe pads are connected to the circuit layer connected to the corresponding electrode pads.
In inspecting the semiconductor device, the probes of an inspection instrument are brought into contact with the probe pads arranged in combination respectively with the electrode pads to avoid damaging the electrode pads and the circuit layer formed under the electrode pads. Since the inspection does not damage the semiconductor device, mounting a faulty semiconductor device on a lead frame is obviated.
Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
Figure 1 is a fragmentary perspective view of a semiconductor device in a first embodiment according to the present invention mounted on a film carrier;
Figure 2 is a fragmentary plan view of a semiconductor device in a second embodiment according to the present invention;
Figure 3 is a fragmentary plan view of a semiconductor device in a third embodiment according to the present invention;
Figure 4 is a fragmentary plan view of a semiconductor device in a fourth embodiment according to the present invention;
Figure 5 is a fragmentary plan view of a semiconductor device in a fifth embodiment according to the present invention;;
Figure 6 is a fragmentary sectional view of a semiconductor device in a sixth embodiment according to the present invention;
Figure 7 is a perspective view of a conventional semiconductor device;
Figure 8 is a schem2tic side elevation showing a mounting con figuratior. formed by a wire bonding method;
Figure 9 is a schematic side elevation showing a mounting configuration formed by a TAB method;
Figure 10 is a sectional view showing a mounting configuration formed by using a double coated adhesive tape; and
Figure 11 is a fragmentary sectional view of a conventional semiconductor device.
First ##rbodiment (Fig. 1)
A semiconductor device in a first embodiment according to the present invention is formed in a semiconductor chip 20 having the shape of a plate similar to that of the conventional semiconductor device shown in Fig. 7. A protective layer 21 and electrode pads 22 are formed on the upper surface of the semiconductor chip 20. The electrode pads 22 are formed in the periphery of the upper surface along the edges of the same at predetermined intervals greater than the width of the electrode pads 22.
The semiconductor chip 20 has a circuit layer fabricated on a semiconductor crystal substrate by a plurality of processes. The processes may be conventional processes including an oxide film forming process, an impurity diffusion process, an ion implanting process, a CVD (chemical vapor deposition) process, a vapor deposition process and a sputtering process. The internal construction of the semiconductor chip 20 is similar to that of the conventional semiconductor device shown in
Fig. 11.
The semiconductor device is different from the conventional sem concuctor device 1 in that a probe pad 24 is formed near each electrode pad 22 and is electrically connected to the electrode pad 22 by a bridge 23. The probe pads 24 and the bridges 23 are formed of the same material as that forming the electrode pads 22. Although it is preferable to form the probe pads 24 on a protective layer 21 formed on the upper surface of the semiconductor chip 20, the probe pads 24 may be formed simultaneously with the electrode pads 22. In simultaneously forming the electrode pads 22 and the probe pads 24, portions of the protective layer 21 corresponding to both the electrode pads 22 and the probe pads 24 are removed.
In using the semiconductor device, current is supplied through the electrode pads 22 or the probe pads 24 to the semiconductor device.
The electric characteristics of the semiconductor device thus fabricated are inspected with an inspection instrument, such as an automatic wafer prober, in which the probes 25 of the inspection in instrument are brought into contact with the probe pads 24. In inspecting the semiconductor device with the inspection instrument, i.e., the automatic wafer prober, in come cases, some of the probes 25 are pressed against the probe pads 24 at an extraordinary pressure due to the inappropriate adjustment of probe pressure or due to the misalignment of the semiconductor device relative to the automatic wafer prober.
However, the protective layer 21 underlying the probe pads 24 withstands the extraordinary pressure to protect the circuit layer underlying the protective layer 21 from being fissured or damaged. Even if the probe pads 24 are formed on the same layer as the electrode pads 22 by removins portions of the protective layer 21, the circuit layer underlying the electrode pads 22 is not stressed and is not damage2 when pressure is applied to the probe pads 24 because the probe pads 24 are dislocated from the positions of the corresponding electrode pads 22.
After being inspected, the semiconductor device is mounted on a film carrier 26 or the luke, and then the leads 27 of the film carrier 26 are connected to bumps formed on the electrode pads 22 as shown in
Fig. 1. Since there is no possibility of fissuring or d#gin# the electrode pads 22 and the insulating layer underlying the electrode pads 22 in connecting the leads 27 of the film carrier 26 to the bumps on the electrode pads 22, the semiconductor device in perfect condition is mounted on the film carrier 26.
Since the probes 25 are brought in contact with the probe pads 24 in inspecting the semiconductor device and hence the electrode pads 22 have smooth, flat surfaces, the bumps 28 are in firm contact with the electrode pads 22 to ensure the perfect electrical connection of the electrode pads to the leads 27 of the film carrier 26.
Second Embodiment (Fig. 2)
Referring to Fig. 2, a semiconductor chip 20 is provided on its upper surface with a plurality of electrode pads 22, and a plurality of probe pads 24 arranged near the electrode pads 22 on the inner side of the same and connected to the electrode pads 22 by bridges 23, respectively. The probe pads 24 may be arranged near the electrode pads 22 on the outer side of the same, respectively.
Third Embodiment (Fig. 3)
Referring to Fig. 3, a semiconductor chip 20 is provided in the periphery of its upper surface with electrode pads 30 and probe pads 31 alternately arranged along the edges thereof at predetermined intervals.
The probe pads 31 are not electrically connected to the corresponding electrode pads 30 on the upper surface of the semiconductor chip 20.
The probe pads 31 may be connected to the corresponding electrode pads 30 within the semiconductor chip 20 or may directly be connected to the terminals of the circuit layer to which the corresponding electrode pads 30 are connected, respectively.
Fourth Embodiment (Fig. 4)
Referring to Fig. 4, a semiconductor chip 20 is provided in the periphery of its upper surface with electrode pads 40 arranged at intervals smaller than the width thereof, and probe pads 41 arranged on the inner side of the electrode pads 40 near the same, respectively.
The prove pads 41, similarly to the probe pads 31 of the semiconductor device in the third embodiment, may be connected to the electrode pads 40 within the semiconductor chip 20 or may directly be connected to terminals of the circuit layer to which the corresponding electrode pads 40 are connected.
Fifth Embodiment (Fig. 5)
Referring to Fig. 5, a semiconductor chip 20 is provided in the periphery of its upper surface with electrode pads 50 arranged at intervals greater than the width thereof, and probe pads 51 arranged on the inner side of the electrode pads 50 at positions each corresponding to the middle between the adjacent electrode pads 50 so that the elec trode pads 50 and the probe pads 51 are arranged zigzag.
Sixth Embodiment (Fig. 6)
Referring to Fig. 6, a semiconductor chip 20 is provided on either its upper surface or its lower surface, for example, on the upper surface, with electrode pads 60, and probe pads 61 on the other surface, for ex#mple, the lower surface, of the semiconductor chip 2C. The electrode pads 60 and the corresponding probe pads 61 are connected by bridges 62 penetrating the semIconductor chip 20, respectively.
Although the invention has been described in its preferred forms with a certain degree of particularity, obviously, many changes and variations are possible therein. It is therefore to be understood that the present invention may be practiced otherwise than as specifically described herein without departing from the scope and spirit thereof.
Claims (3)
1. A semiconductor device formed in a semiconductor chip, comprising a circuit layer, and a plurality of electrode pads formed on either one surface or the other of the semiconductor chip and connected to the circuit layer,
characterized in that probe pads are formed near and in combination with the electrode pads, respectively, and are connected to the circuit layer connected to the corresponding electrode pads.
2. A semiconductor device formed in a semiconductor chip, comprising a circuit layer, and a plurality of electrode pads formed on either one surface or the other of the semiconductor chip and connected to the circuit layer,
characterized in that probe pads are formed on the upper surface of the semiconductor chip in combination with the electrode pads formed on the lower surface of the semiconductor chip, respectively, probe pads are formed on the lower surface of the semiconductor chip in combination with the electrode pads formed on the upper surface of the semiconductor chip, and the probe pads are connected to the circuit layer connected to the corresponding electrode pads.
3. A semiconductor device substantially as hereinbefore described with reference to, and as illustrated by, the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2146790A JPH0439950A (en) | 1990-06-05 | 1990-06-05 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9111855D0 GB9111855D0 (en) | 1991-07-24 |
| GB2244864A true GB2244864A (en) | 1991-12-11 |
| GB2244864B GB2244864B (en) | 1995-01-18 |
Family
ID=15415599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9111855A Expired - Fee Related GB2244864B (en) | 1990-06-05 | 1991-06-03 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH0439950A (en) |
| GB (1) | GB2244864B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0907207A2 (en) * | 1997-08-27 | 1999-04-07 | Nec Corporation | Semiconductor device having alternating long and short contact pads with a fine pitch |
| WO2005117109A1 (en) * | 2004-05-28 | 2005-12-08 | Koninklijke Philips Electronics N.V. | Chip having two groups of chip contacts |
| US20120068324A1 (en) * | 2009-04-15 | 2012-03-22 | Olympus Medical Systems Corp. | Semiconductor device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4745007B2 (en) * | 2005-09-29 | 2011-08-10 | 三洋電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP5242063B2 (en) * | 2006-03-22 | 2013-07-24 | 株式会社フジクラ | Wiring board manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2177253A (en) * | 1985-06-28 | 1987-01-14 | Gen Electric Co Plc | Electrical interconnection arrangement |
| WO1989011659A1 (en) * | 1988-05-16 | 1989-11-30 | Leedy Glen J | Novel method of making, testing and test device for integrated circuits |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62274632A (en) * | 1986-05-22 | 1987-11-28 | Hitachi Ltd | Small substrate for inspection and usage thereof |
| JPH0281454A (en) * | 1988-09-19 | 1990-03-22 | Hitachi Ltd | Semiconductor integrated circuit device and method of testing the same |
| JPH07109842B2 (en) * | 1989-06-09 | 1995-11-22 | 株式会社東芝 | Tape carrier testing method |
| EP0457013A3 (en) * | 1990-04-16 | 1992-03-04 | National Semiconductor Corporation | Ferroelectric capacitor test structure for chip die |
-
1990
- 1990-06-05 JP JP2146790A patent/JPH0439950A/en active Pending
-
1991
- 1991-06-03 GB GB9111855A patent/GB2244864B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2177253A (en) * | 1985-06-28 | 1987-01-14 | Gen Electric Co Plc | Electrical interconnection arrangement |
| WO1989011659A1 (en) * | 1988-05-16 | 1989-11-30 | Leedy Glen J | Novel method of making, testing and test device for integrated circuits |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0907207A2 (en) * | 1997-08-27 | 1999-04-07 | Nec Corporation | Semiconductor device having alternating long and short contact pads with a fine pitch |
| EP0907207A3 (en) * | 1997-08-27 | 1999-05-06 | Nec Corporation | Semiconductor device having alternating long and short contact pads with a fine pitch |
| US6008542A (en) * | 1997-08-27 | 1999-12-28 | Nec Corporation | Semiconductor device having long pads and short pads alternated for fine pitch without sacrifice of probing |
| WO2005117109A1 (en) * | 2004-05-28 | 2005-12-08 | Koninklijke Philips Electronics N.V. | Chip having two groups of chip contacts |
| US9318428B2 (en) | 2004-05-28 | 2016-04-19 | Nxp B.V. | Chip having two groups of chip contacts |
| US20120068324A1 (en) * | 2009-04-15 | 2012-03-22 | Olympus Medical Systems Corp. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9111855D0 (en) | 1991-07-24 |
| JPH0439950A (en) | 1992-02-10 |
| GB2244864B (en) | 1995-01-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19950603 |