GB2154061A - Methods of manufacturing semiconductor circuit devices - Google Patents

Methods of manufacturing semiconductor circuit devices Download PDF

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Publication number
GB2154061A
GB2154061A GB08502454A GB8502454A GB2154061A GB 2154061 A GB2154061 A GB 2154061A GB 08502454 A GB08502454 A GB 08502454A GB 8502454 A GB8502454 A GB 8502454A GB 2154061 A GB2154061 A GB 2154061A
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Prior art keywords
semiconductor
type
film
conductivity type
region
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GB08502454A
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GB2154061B (en
GB8502454D0 (en
Inventor
Setsuo Oguro
Shizuo Kondo
Makoto Furihata
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Hitachi Ltd
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Hitachi Ltd
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Publication of GB2154061A publication Critical patent/GB2154061A/en
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Publication of GB2154061B publication Critical patent/GB2154061B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H01L27/0244—I2L structures integrated in combination with analog structures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H03K19/01818—Interface arrangements for integrated injection logic (I2L)

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

A method of manufacturing a semiconductor circuit device begins by providing two wells (3, 4) in a semiconductor substrate, each of these wells being of the opposite conductivity type to the substrate (2). The surface of the substrate is then oxidised and subsequently an I<2>KL circuit is formed in one (3) of the well regions. Finally, a MISFET circuit is formed in the second well region (4). This method allows the impurity concentrations in the two well regions to be controlled separately, thus giving improved electrical characteristics. <IMAGE>

Description

1 GB 2 154 061 A 1
SPECIFICATION
Methods of manufacturing semiconductor circuit devices The present invention relates to a method of manufacturing a semiconductor integrated cir cuit device having a complementary insulated gate field effect transistor circuit and an inte grated injection logic circuit on the same 75 semiconductor substrate.
In prior art publications concerned with a
CMISFET-12L IC such as United States Patent No. 4122481 or Japanese Patent Laid-Open No. 52482/1979, the CMISFET-12 L IC is manufactured by a complicated process. Therefore, attempts have been made to form those semiconductor regions which constitute the CMISFET circuit and those semiconductor regions which constitute the 12 L circuit using the same steps as far as possible. For example, according to Japanese Patent LaidOpen No. 52482/1979, the well region for the 12 L and the well region for an N- channel MOSFET are formed simultaneously.
In a CMISFET-I'L obtained by the above mentioned method, however, the electrical characteristics of either the CMISFET or the 12 L must be sacrificed.
According to a study conducted by the 95 inventors of the present invention, in order to improve the electrical characteristics without reducing the degree of integration, it was confirmed that the impurity concentration plays a very important role in the emitter region of the inverse transistors that operate as driver transistors in the I'L, and in the semiconductor region (well region) where channels are formed in the CMISFET among the plurality of semiconductor regions that constitute the integrated circuit. These inverse transistors each have a collector region, a base region and an emitter region that are formed in the semiconductor substrate in that order from the main surface toward the inside of the substrate. Thus the inverse transistor is constructed in the opposite way to an ordinary transistor, which is why it is so called.
When forming the emitter and well regions simultaneously, if the impurity concentration is increased in order to increase the current amplification factor 13i of the inverse transis tors in an 12 L, the operating frequency of the CMISFET decreases. That is, if the impurity concentration in the well region is high, the depletion layer spreads less easily. Therefore, the junction capacity increases so that the switching operations of the CMISFET are no longer capable of following high-frequency signals. To increase the operating frequency, the gate width of the MISFETs must be in creased to increase the current capacity.
Therefore, the MISFETs occupy an increased area, and the degree of integration decreases.
On the other hand, if the impurity concentra- 130 tions in these regions are small in order to improve the operating frequency of the CIVIISFET, the current amplification factor i becomes small, the operating speed of the I'L decreases, and the power consumption increases.
In Japanese Patent Laid-Open No. 52482/1979, the source and drain regions of the MISFETs are formed prior to the formation of the gate electrodes, and are not selfaligned relative to the gate electrodes. Similarly, the well region in the 12L and the semiconductor region formed in the well region are not self-aligned, either. Therefore, a sufficient masking margin must be provided. Accordinly, it becomes difficult to obtain CIVIISFET- 12 L ICs in a highly integrated form.
An embodiment of the invention will now be described, by way of example, with refer- ence to the accompanying drawings, in which:
Fig. 1 is a sectional view of an integrated circuit produced by the embodiment; Figs. 2A to 2H are sectional views of the steps comprising the embodiment.
Fig. 1 is a diagram showing the construction of a CIVIISFET- 12 L IC fabricated according to an embodiment of the present invention, in which the region X, shows the construction of the complementary MISFETs, and the region X2 shows the construction of the 12 L elements.
As shown in Fig. 1, unlike conventional devices, the integrated circuit of this embodiment makes use of a substrate which is pre- pared by growing a p-type epitaxial layer 2 of a low impurity concentration on a p-type silicon substrate 1 of a low impurity concentration. Reference number 16 denotes an n - type buried layer formed under the well re- gion that will form the 12 L circuit, 3 denotes a first n-type well region of a low concentration formed in the p-type layer 2, and 4 denotes a second n-type well region having an impurity concentration smaller than that of the first n- type well region 3. An 12 L consists of a p-type injector region 5, a p- type base region 6 of an npn inverse transistor, an n ±type collector region 7 of the npn inverse transistor and an n ±type emitter contact region 8 formed in the first n-type well region 3. The n-type well region 3 forms an emitter region for the npn inverse transistor. A p-channel MISFET consists of p '- type source and drain regions 9 formed in the second n-type well region 4, a gate insulation film 11, and a polycrystalline silicon layer 14 that serves as a gate electrode. An n-channel MISFET consists of ntype source and drain regions 10 formed in the p--type layer where no well region is formed, a gate insulation film 12, and a polycrystalline silicon layer 15 that serves as a gate electrode.
Figs. 2A to 2H are diagrams illustrating the process for producing the integrated circuit of Fig. 1. Complementary MIEFETs are formed 2 GB 2 154061 A 2 in the area X, and 12 L elements are formed in the area X2.
Referring to Fig. 2A, first, n-type impurities such as arsenic impurities are selectively intro- duced into a predetermined portion of a ptype silicon substrate 1 by diffusion techniques or ion implantation techniques, and ptype doped silicon is deposited on the substrate by epitaxial growth to form a p-- type layer 2 (impurity concentration N: 1015 ato MS/CM3). At the same time, an n '-type buried layer 16 is also formed owing to the diffusion of the n- type impurities.
As shown in Fig. 2B, an n-type well region 4 is selectively formed in the p -type layer 2 in order to form p-channel MISFETs. In order to selectively form the n-type well region 4, an oxide film 30 of a thickness of 500 angstroms is first formed by thermal oxidation on the whole surface of the p-type epitaxial layer 2, and an SO, film 31 of a thickness of 1500 angstroms is formed thereon by the chemical vapor deposition method (hereinafter referred to as the CVD method). Then the oxide film 30 on that portion where the n-type well region is to be formed and the Si,N, film 31, are selectively removed by plasma etching using a photoresist film (not shown) as a mask, such that the surface of the p-type epitaxial layer 2 is exposed. Masks for forming all the n-type well regions are completed in this step so that all the positions of all the well regions are determined by the masks. Thereafter, the windows for forming the ntype well regions that form the low-concentration 12 L are covered with a suitable mask such as a thick photoresist film 32 as shown in Fig. 25, and n-type impurities such as phosphorus ions are implanted (N: 1011 atoms /CM3) to form the n --type well region 4 which has a low impurity concentration. Although the impurity concentration is low, the well region 4 should preferably be formed by the ion implantation method since it is possible to con- trol the concentration precisely.
Then, the low-concentration n-type well region 3 is formed as shown in Fig. 2C. After the photoresist film 32 is removed, the n-type well region 4 is covered with a thick photoresist film 33, and n-type impurities such as phosphorus ions are implanted (N: 107 atoms/ CM3) to form the lowconcentration ntype well region 3. The well region 3 should preferably be formed by the ion implantation technique since it is possible to control the impurity concentration precisely as mentioned above.
A field oxide film is then formed as shown in Fig. 2D. After the photoresist film 33, the
S'3N4 film 31 and the S'02 film 30 are removed in succession, an oxide film (S'02 film) 34 of a thickness of 500 angstroms is formed by thermal oxidation on the exposed surfaces of the epitaxial layer 2, and then an SO, film 35 of a thickness of 1500 ang- stroms is formed by the CVD method. The SO, film 35 is then selectively removed by plasma etching using a photoresist film (not shown) as a mask, so that the SiO, film 34 is partially exposed. To prevent the formation of an inversion layer under the field oxide film under this condition, p-type impurities such as boron ions are implanted while the photoresist film is still in place. The photoresist film is then removed, and a field oxide film (SiO, film) 17 is formed by thermal oxidation to a thickness of 9000 angstroms using the Si,N., film 35, which is not permeable to oxygen, as a mask.
Then, as shown in Fig. 2E, the gate insulation films and the gate electrodes of the MISFETs are formed. After the SiO-, film 34 and the SO, film 35 are removed, a gate insulation film (SiO, film) is formed to a thickness of 500 angstroms by thermal oxidation on the whole surface of the exposed epitaxial layer 2. A polycrystalline silicon layer is then formed to a thickness of 3500 angstroms on the whole surface of the substrate by the CVD method. Phosphorus impurities are introduced into the polycrystalline silicon layer by diffusion to decrease its sheet resistance to such a level that it can be used as gate electrodes. To complete the gate elec- trodes, the polycrystalline silicon layer and the gate insulation film are selectively removed by plasma etching using a photoresist film as a mask. The gate insulation films 11, 12 and the gate electrodes 14,15 of the MISFETs are thus completed. At the same time, the surface of the epitaxial layer 2 on the I'L side is exposed.
Next, a p-type semiconductor region is formed as shown in Fig. 2F. First, to prevent the exposed epitaxial layer 2 from being contaminated, an S'02 film 25 is formed to a thickness of 100 to 200 angstroms by thermal oxidation on the surface of the epitaxial layer 2, and also on the surfaces of the polycrystalline silicon layers 14,15. Then an Si02 film 36 is formed to a thickness of 1500 angstroms by the CVD method. The S'02 film 36 is selectively removed by plasma etching using a photoresist film (not shown) as a mask, to complete the mask for forming the ptype regions. When forming the mask 36, the processing with photoresist does not require so high a precision. That is, the mask may be slightly shifted provided that its ends 36a,36b and 36c are on the field oxide film 17. Then p-type impurities such as boron ions are implanted (or diffused) into the surfaces of the ntype well regions 3,4 not covered by the polycrystalline silicon layer 14, the field oxide film 17 and the mask 36, in order to form the p-type regions 5 and 6 that serve as the injector and base of the 12L, and to form the pl-type source and drain regions 9 of the pchannel MISFETs. As will be obvious from Fig. 2F, the p-type region 5 is self-aligned by 3 GB 2 154 06 1 A 3 the field oxide film 17, and the p±type source and drain regions 9 are self-aligned by the field oxide film 17 and by the polycrystalline silicon 14.
Next, as shown in Fig. 2G, n-type semiconductor regions are selectively formed in the epitaxial layer 2 and in the n-type well region 3. First, the S'02 film 36 is removed, and a new Si02 film 37 is formed to a thickness of 1500 angstroms by the CVD method. The S'02 film 37 is then selectively removed by plasma etching using a photoresist film (not shown) as a mask, to complete the mask for forming the n-type regions. When forming the mask 37, the processing with Photoresist does not require a high precision, as when forming the mask 36. Then n-type impurities such as phosphorus ions are implanted into the surface of the epitaxial layer 2 where the polycrystalline silicon layer 15 and the field oxide film 17 have not been formed, and into the surface of the well region 3 where the mask 37 and the field oxide film 17 have not been formed, thereby forming the emitter contact region 8 of the I'L, and the n '--type source and drain regions 10 of the n-channel MISFETs.
Next, an n-type collector region is formed as shown in Fig. 2H. That is, after the SiO, film 37 is removed, a new SiO, film 38 is formed to a thickness of 1500 angstroms by the CVD method. The SiO, film 38 is then selectively removed by plasma etching using a photoresist film (not shown) as a mask, to complete the mask for forming the n-type collector region. Then n-type impurities such as phosphorus ions are introduced by implantation (or diffusion) to form an n-type collector 7.
After the SiO, film 38 is removed, an SiO, film 18 (see Fig. 1) is formed on the whole surface of the substrate to a thickness of 1500 angstroms as an interlayer insulation film by the CVD method. After contact holes have been formed in the SiO, film 18, aluminum is deposited thereon to a thickness of 8000 angstroms by the vacuum evaporation method. The aluminum layer is patterned to the desired shape to form the aluminum elec- trodes 19 to 24 that are in ohmic contact with each region. Thus, the CMISFETI'L IC of the construction shown in Fig. 1 is completed.
According to this construction, use is made of a p -type silicon layer of a low impurity concentration as a substrate, and the 12 L circuit and the p-channel MISFETs are formed in the n-type well regions that are separately formed in the substrate. Therefore, the impurity concentration can be controlled for each of the well regions. By making the impurity concentration in the n-type well re gion 3 on the 12 L side greater than the im purity concentration of the well region 4, therefore, the inverse current amplification factor [3i of the inverse transistors in the 12L 130 circuit can be enhanced to realize a 12 L which operates at high speeds and which consumes a reduced amount of electric power. With the impurity concentration being made low in the n-type well region 4 on the p-channel MISFET side, furthermore, high- speed operation can be realized even when the gate width of the MISFET is reduced. Accordingly, the chip size can be reduced but the high-speed operation is maintained.
Further, as will be obvious from the method of manufacturing the integrated circuits explained in conjunction with Figs. 2A to 2H, the well regions 3,4 are formed in the epitax- ial layer 2 before forming the field oxide film 17 by the selective oxidation technique. In the well region 4 constituting the 12 L, therefore, a field oxide film can be formed in the 12 L elements to prevent the formation of parasitic transistors. The surface of the well region 3 under such a thick field oxide film is difficult to invert. Therefore, a wide range of powersupply voltages can be applied, and increased freedom is provided for laying out the wiring.
Further, the surface of the well region 4 is also difficult to invert. Accordingly, the abovementioned advantages are brought about.
When forming the CMISFETs, furthermore, employment of the silicon gate processing technique makes it possible to obtain a CMISFET- 12 L IC of a high density.
The invention can further be put into practice in a variety of ways and is not limited to the embodiment described. The high impurity concentration n-type well region where the 12L circuit will be formed, may be formed in the following manner. Ions are implanted simultaneously with the formation of the n-type well region 4 where the p-channel MISFETs will be formed, and ions are again implanted into the well region 3 while the well region 4 is covered by a mask- The above-mentioned order may of course be reversed. Further, the conductivity types of the semiconductor re- gions may be reversed.
Another possibility is to have a process wherein the 12 L circuit is formed in an epitaxial layer that is grown on the substrate, and the nchannel MISFETs are formed in the epitaxial layer, in order to increase the local impurity concentration in the epitaxial layer where the 12L circuit will be formed. That is, use is made of epitaxial layers that are insulated and separated as semiconductor regions that correspond to the well regions in the aforementioned embodiments, and the impurity concentrations are changed.
This application was divided out of U.K. Patent Application NO. 82.27060 (Published under No. 2107117) and contains matter also described in that application. Also divided out of that application was U.K. Patent Application NO ----- ------ Attention is drawn to these applications.
4 GB 2 154061 A 4

Claims (3)

1. A method of manufacturing semiconductor integrated circuit devices comprising:
(a) a step of preparing a substrate of a semiconductor of a first conductivity type; (b) a step of forming first and second semiconductor regions in said semiconductor, said first and second semiconductor regions being separated from each other and being of a second conductivity type that is opposite to said first conductivity type; (c) a step of selectively oxidizing the semiconductor of said first conductivity type after said step (b) has been completed; (d) a step of forming a plurality of third semiconductor regions having the first conductivity type in said first semiconductor region to form the elements of an 12L circuit; and (e) a step of forming a plurality of fourth semiconductor regions having the first type of conductivity in said second semiconductor region to form the elements of a MISFET circuit.
2. A method of manufacturing semiconductor integrated circuit devices according to claim 1, wherein the first semiconductor region is formed by introducing impurities of the second conductivity type into the semiconductor of the first conductivity type such that the impurity concentration therein becomes greater than the impurity concentration in the second semiconductor region.
3. A method of manufacturing semiconcluctor integrated circuit devices according to claim 2, wherein said impurities are introduced by implanting ions.
Printed in the United Kingdom for Her Majesty's Stationery Office, Dd 8818935, 1985. 4235Published at The Patent Office, 25 Southampton Buildings. London, WC2A lAY, from which copies may be obtained-
GB08502454A 1981-09-24 1985-01-31 Methods of manufacturing semiconductor circuit devices Expired GB2154061B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56149433A JPS5851561A (en) 1981-09-24 1981-09-24 Semiconductor integrated circuit device

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GB8502454D0 GB8502454D0 (en) 1985-03-06
GB2154061A true GB2154061A (en) 1985-08-29
GB2154061B GB2154061B (en) 1986-04-09

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GB08227060A Expired GB2107117B (en) 1981-09-24 1982-09-22 Semiconductor integrated circuit devices
GB08502454A Expired GB2154061B (en) 1981-09-24 1985-01-31 Methods of manufacturing semiconductor circuit devices
GB08502453A Expired GB2154060B (en) 1981-09-24 1985-01-31 Semiconductor integrated circuit devices

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GB08227060A Expired GB2107117B (en) 1981-09-24 1982-09-22 Semiconductor integrated circuit devices

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Application Number Title Priority Date Filing Date
GB08502453A Expired GB2154060B (en) 1981-09-24 1985-01-31 Semiconductor integrated circuit devices

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JP (1) JPS5851561A (en)
DE (1) DE3235409A1 (en)
FR (2) FR2514200A1 (en)
GB (3) GB2107117B (en)
HK (2) HK69187A (en)
IT (1) IT1153730B (en)
MY (1) MY8700644A (en)
SG (1) SG40887G (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5955052A (en) * 1982-09-24 1984-03-29 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JPS60253261A (en) * 1984-05-29 1985-12-13 Clarion Co Ltd Integrated circuit containing iil element
JPH0387403A (en) * 1989-08-31 1991-04-12 Mitsubishi Electric Corp Snow melting device
JP2550736B2 (en) * 1990-02-14 1996-11-06 三菱電機株式会社 Snow melting equipment
KR920015363A (en) * 1991-01-22 1992-08-26 김광호 TTL input buffer circuit

Citations (1)

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Publication number Priority date Publication date Assignee Title
US4258379A (en) * 1978-09-25 1981-03-24 Hitachi, Ltd. IIL With in and outdiffused emitter pocket

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Publication number Priority date Publication date Assignee Title
US3594241A (en) * 1968-01-11 1971-07-20 Tektronix Inc Monolithic integrated circuit including field effect transistors and bipolar transistors,and method of making
IT947674B (en) * 1971-04-28 1973-05-30 Ibm EPITAXIAL DIFFUSION TECHNIQUE FOR THE MANUFACTURE OF TRANSISTIC BIPOLAR RI AND FET TRANSISTORS
JPS52117086A (en) * 1976-03-29 1977-10-01 Sharp Corp Semiconductor device for touch type switch
JPS52156580A (en) * 1976-06-23 1977-12-27 Hitachi Ltd Semiconductor integrated circuit device and its production
US4429326A (en) * 1978-11-29 1984-01-31 Hitachi, Ltd. I2 L Memory with nonvolatile storage
JPS5611661A (en) * 1979-07-09 1981-02-05 Sankyo Seiki Mfg Co Ltd Magnetic card reader of normal card containing type
JPS56116661A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
US4258379A (en) * 1978-09-25 1981-03-24 Hitachi, Ltd. IIL With in and outdiffused emitter pocket

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Publication number Publication date
FR2514200A1 (en) 1983-04-08
GB8502453D0 (en) 1985-03-06
HK69187A (en) 1987-10-02
GB2154060B (en) 1986-05-14
IT8223326A0 (en) 1982-09-17
GB2107117B (en) 1986-04-09
MY8700644A (en) 1987-12-31
FR2514200B1 (en) 1984-07-27
IT1153730B (en) 1987-01-14
GB2107117A (en) 1983-04-20
GB2154061B (en) 1986-04-09
SG40887G (en) 1987-07-17
GB2154060A (en) 1985-08-29
HK69887A (en) 1987-10-02
FR2533367A1 (en) 1984-03-23
FR2533367B1 (en) 1986-01-24
DE3235409A1 (en) 1983-04-14
GB8502454D0 (en) 1985-03-06
JPS5851561A (en) 1983-03-26

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Effective date: 19940922