JPS60253261A - Integrated circuit containing iil element - Google Patents

Abstract

PURPOSE:To realize characteristics desirable to both a first one conductive type semiconductor region and a second one conductive type semiconductor region by isolating the first region and the second region having impurity concentration higher than that of the first region by an other conductive type semiconductor region and forming an IIL element in the second region and an analog element in the first region. CONSTITUTION:An N<+> type region 14 and impurity layers 15B, 15C having concentration higher than that of the region 14 are shaped, and an N type layer 16 is grown on the whole surface. P type regions 18A, 18B are formed so as to surround N<+> type regions 17A, 17B by thermally treating a substrate 11. Consequently, the N type layer 16 is isolated into two regions 16A, 16B. A P type impurity is diffused to each shape P type regions 19A, 19B and 19C in the N<+> type region 17A and the N type region 16B. An N type impurity is diffused to severally form N<+> type region 20A, 20B and 20D in the P type regions 19B and 19C, and N<+> tyep regions 20C and 20E are shaped in the N<+> type region 17A and the N type region 16B. An I<2>L element is formed in one N<+> type region 17A isolated by the P type region 18A, and an N-P-N Tr as an analog element is shaped in the other N type region 16B.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit including an IIL component that can achieve both desired characteristics of an IIL device and an analog device.

The IIL (Integrated Injection Logic, hereinafter referred to as I2L) element is K as shown in Figure 1.
By combining PNP transistor Q1 and NPN) transistor Q2, the device structure is simplified,
It is a bipolar type WA embedded circuit that allows for high integration in terms of manufacturing process and reduces power consumption.

In addition, since IL can be used in common with conventional analog ICs in terms of process, it is widely used in analog/digital A/54 ICs.

FIG. 2 is a cross-sectional view showing the conventional structure of such a hybrid IC, in which 1 is a P-type conductor substrate, 2A and 2B are embedding regions, and 4 is a P-type conductor substrate.
A and 4B are P-type regions 3A and 3B.

N-type region separated by m by 3C, 5A to 5C are Pfj
The J image area, 6A to 6E, is the Nm area. Here, NPN transistors are formed as IL elements and analog elements in the island regions A and 8 corresponding to the N-type regions 4A and 48, respectively. In the I L element, ■ is the injector sc
i t c24X multicollector, B is the base, E is the emitter, and in an NPN transistor, Em is the emitter, B is the base, and C is the collector.

In such conventional hybrid ICs, I″L has excellent features as mentioned above, but on the other hand, it has five drawbacks that make it one step slower than other logic circuits in terms of switching speed.The reason is In the structure shown in Figure 2, N becomes the emitter E.
This is because minority carriers are accumulated in the emitter E because the impurity concentration in the type region 4A is low. In order to eliminate this drawback, the impurity concentration of the N type region 4A can be increased, but this N type region 4A is the collector region 4 of the NPN transistor (NPNTr) which is an analog element.
Since it is formed in the same process as B, its impurity concentration is determined based on the characteristics of the pixel element. Here, N type region 4
A and 4B have a contradictory relationship in terms of characteristics, and NPN
In order to increase the collector breakdown voltage of the Tr, the lower the impurity concentration, the better.

Therefore, the impurity concentration χ cannot be determined solely based on IL considerations. For this purpose, it is conceivable to form the N-type regions 4A and 4B independently in a manner convenient for each, but this is not practical since the process would be extremely complicated.

31 The present invention has been made from the above point of view, and it is an object of the present invention to provide an integrated circuit including an IIL element that can realize desirable characteristics for both the IIL element and the analog element.

The present invention is characterized in that the first conductivity type conductor region and the second first conductivity type conductor region having a higher impurity concentration are separated by the conductor region in the mold, and the second conductor region is separated by the conductor region in the mold. The integrated circuit includes an IIL element configured such that an IIL element is formed in a first conductive type conductor region and an analog element is formed in the first conductive type conductive region.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a cross-sectional view showing an integrated circuit including an IIL element according to an embodiment of the present invention, in which 11 is a P-type silicon substrate, 14 is an N-type buried region, and 16A and 16B are N-type silicon substrates separated by a P-type region 18A. The regions 17A and 17B are the P-type regions 18
N separated from N-type regions 16A, 16B by A
The m region has a higher impurity concentration than those of the N type regions 16A and 16B.

19 A to 19B are the above Nff1l regions 17 A fP
3VC is formed in the Pffi region, 19C is formed in the Nm region 16B; and 20E are the above Nm regions 17A, respectively.
and an Nm region formed in the N-type region 16B, 21
A to 21H are 1! where each area Ilc is provided! It is extreme.

In the above configuration, an IL element is formed in the power N type region 17AK separated by the P type region 18A, and an NP as an analog element is formed in the other N type region 16B.
NTr is formed. Here, the impurity concentrations of the N-type region 17A and the Nm region 16B are set to values that provide desirable characteristics as an IL resistor and as an analog element, respectively.

FIG. 4 (at to (jl) is a cross-sectional view showing a method for manufacturing an integrated circuit having the structure shown in FIG. 3, and the steps will be explained below in order of process with reference to the drawings.

Step (a): As shown in FIG. 4 (at), a PM silicon single crystal substrate 11i is prepared, oxidized to form a silicon dioxide (Sing) film 12A on its surface, and then a well-known photolithography method is applied. A window 13A is provided in a part of the 5i02 film 12A.

Step (bl: As shown in FIG. 4 (bl), an N-type impurity such as arsenic (As) is selectively diffused from the window 13A to form an N-type region 14 which is to be buried by the root. At the same time as the diffusion process or Through the subsequent oxidation treatment, the window 13A becomes Si again.
Treated with 02mA.

Work a (C1: As shown in Fig. 4 (C1), the above board 11fi
5i02Jii12A of the surface is selectively 11tiiei to form [13B, iac.

Engineering I (di: Figure 4 (di ), J: Sea urchin, above window 13
8,130 Nff1 impurities such as arsenic (As) and P-type impurities such as boron (8) are introduced to form an impurity layer 158.
, 150. Arsenic impurity 1 degree above (bl
Higher than its concentration in the process (select.

Process (el: As shown in Fig. 4 (el), Si02 film 12
After completely removing A, a Nm layer 16 is grown on the entire surface by epitaxial method.

Step I (fl: As shown in FIG. 4, the substrate 11 is subjected to heat treatment to form an N-type region 17At17B and P-type regions 18A and 188Y.The heat treatment removes arsenic and Boron diffuses into the N-type layer 16 and reaches El, but at this time, boron has a diffusion constant 7.C thicker than arsenic, so it spreads widely, so it surrounds the N-type regions 17A and 178. PM regions 18A, 18B are formed in. As a result, the N-type layer 16 is separated into two regions 16A, 168, and the N-type regions 17A, 17B are also divided into P-type regions 18A, 1.
8B separates them from the Nm regions 16A and 16B.

5i02-12B is formed on the surface again.

Step (g): Figure 4 (as in gl, the above S i02
A window is selectively opened in the film 12B, and P-type impurities such as boron (8) are diffused through the window to form the N-type region 17A.
and P-type regions 19A and 19 in the N-type region 16B, respectively.
B and 19C are formed. The opening of the window is covered with 5i02 film again.

Step (h): As shown in FIG. 4(h), the above 5i02 film 1
2 Selectively open a window on B and link CP from this window)
By diffusing N-type impurities such as
D+ is formed, and Nm regions 2DC and 20g are formed in the Nav region 17A and the Nff1 region 167-8. The aperture area is again covered with 5i02 film.

Engineering N (j): Figure 4 (i) Noyo 5 K, above 5i0
Windows are selectively opened in 2 m 12 B, and a fluzenium film 21 is formed on these windows and 5i02jl12B by vapor deposition or the like.

Engineering@U): As shown in Figure 4 (j), the above aluminum 1
3421 by applying the photorin roughy method to remove unnecessary parts, leaving only the necessary parts and forming electrodes 21 A to 2.
After forming 18, a sintering process is performed.

This completes the integrated circuit having the third factor structure.

According to the integrated circuit 1isK obtained through the above steps, l
L! The particles were formed by arsenic diffusion in step (f) above for 8 hours.
Since it is formed in the sNm region 17A, the impurity concentration can be set to a high value IIcf& to realize the desired characteristics. On the other hand, NPNT which is an analog element
Since r is formed in the N■ region 168P3K formed by the epitaxial growth method in step (e) above, this impurity concentration can be selected independently regardless of the value of the region to be formed in the I''L element. , can be set to a low value to achieve its desired properties.

In the manufacturing method of the present invention, double diffusion of P-type axes and N-type impurities is performed particularly in step 8(f), and a high concentration + N-type region is formed by utilizing the difference in diffusion constant of both impurities. Moreover, a Pm isolation region can be formed at the same time. In this case, since the isolation region is formed by double diffusion, the area can be kept small, which can contribute to integration.

As is clear from the above description, according to the present invention, the first conductivity type cow conductor region and the second first conductivity type cow conductor region having a higher impurity concentration are separated by the second conductivity type cow conductor region. , since the second first conductor region KI IL element is formed and an analog element is formed in the first conductor region, II.
Desirable characteristics can be achieved for both the L resistor and the analog element.

Therefore, the switching speed of the IIL element can be increased, and the breakdown voltage of the analog element will not be lowered.

Note that the conductor type, impurity type, etc. of the conductor region shown in the practical section of the text are all shown, and arbitrary selections and combinations can be made depending on the purpose and use.

[Brief explanation of drawings]

Figure 1 is a circuit diagram for explaining the present invention, Figures 2 and 3 are cross-sectional views showing integrated circuits according to the conventional and embodiments of the present invention, and Figures 4 (a) to (j) are Figure 3. FIG. 3 is a cross-sectional view showing the manufacturing method of the integrated circuit in order of steps. IrL...Integrated injection
Logic confectionery, 16A, 16B...N type area% 17A
. 17B...NfJ region, 18A, 18B...P type isolation region. ll-

Claims (1)

[Scope of Claims] 1. A first conductive type conductor region and a second first conductive type 1 semiconducting region having a higher impurity concentration than the first conductive type conductor region are separated by a second conductive type conductor region, and the above-mentioned II characterized in that an IIL element is formed in the second first conductor region and an analog element is formed in the first conductor region.
An integrated circuit containing L elements. 2. (Step of selectively forming a first conductivity type conductor region on the At fi142 conductivity type semiconductor substrate, (81 selectively forming a first conductivity type impurity and a second conductivity type impurity on the second conductivity type conductor substrate) a step of introducing (Q) a step of forming a first conductivity type conductor layer on the second conductivity type conductor substrate; A second first conductivity type conductor region having a higher impurity concentration than the first conductivity type semiconductor layer is diffused to reach this surface, and a second conductivity type conductor region is formed to surround this region. a step of heat-treating (D) in the second first conductivity type semiconductor region;
A method for manufacturing an integrated circuit including an IIL element, comprising: a step of forming an element; (F) a step of forming another circuit element in the tSt type semiconductor layer; 3. I according to claim 2, characterized in that the 1! type impurity is selected from one having a larger diffusion constant than the first conductive 1! type impurity.
A method for manufacturing an integrated circuit including an IL element.