JPS6148966A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve IIL element performance characteristics by a method wherein a high-concentration epitaxial layer is formed just under the base of a vertical type NPN transistor and a low-concentration epitaxial layer is formed on said high-concentration epitaxial layer. CONSTITUTION:An N<+> type low-resistance buried layer 2 is formed on a P type silicon substrate 1. On the substrate 1, a high-concentration N type epitaxial layer 3-1 is formed, to be followed by the formation of a low-concentration epitaxial layer 3-2 whose impurity concentration is lower than that of the epitaxial layer 3-1. A P<+> type isolating layer 4 is formed by diffusion to be deep enough to reach the substrate 1, which results in the formation of N type islands 5-1, 5-2. On the island 5-1, an injector 7-1 is formed of a P type IIL element, and then a base 7-2 of a vertical NPN transistor. On the island 5-2, a P type diffused layer 8 is formed with its diffusion shallower than the injection 7-1. An IIL element manufactured by this method is superior in performance characteristics to one manufactured by the conventional method.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to I L (I I2L: Intagra
The present invention relates to a method of manufacturing an integrated circuit including InjectionLogic.

The configuration of the conventional example and its problems First, the manufacturing process when manufacturing the entire conventional Pipolar E-C and E-2L circuits on a silicon substrate is shown in Figures 1 (A) to (A).
This will be explained with reference to the process cross-sectional diagram of H). Below, (A)
The items from (H) to (H) are explained in correspondence with the steps (A) to (b) in FIG. 1.

(France) A buried layer 2 is formed on a P-type silicon substrate 1 by thermal diffusion or ion implantation of arsenic or antimony.

(Bj) An n-type single crystal layer 3 is grown on the Si substrate 1.

(c) P+ type isolation diffusion 4 is performed with boron or the like to a depth that reaches the silicon substrate 1 for isolation between transistors, diodes, resistor islands, and isolation from the silicon substrate 2L. This forms isolated islands 5-1.5-2 in this case.

5-1 is a planned area in which bipolar transistors will be formed in all I2L elements 5-2.

Next, in order to produce effects such as lowering the collector resistance of the transistor or the emitter resistance of the I2L element, it is diffused so as to reach the N+ type scattering layer 6 and the C type buried layer 2. This is commonly called collectaol.

(E) Using thermal diffusion or ion implantation, a P-type diffusion layer 7 is formed to form an injector 7-1 of the IL element and a base 7-2 of a vertical NPN transistor of a 2L element. The injector 7-1 has a base of 5-1 and a 7-2ft collector. PNP) corresponds to the emitter of a transistor.

(F') Next, a P-type diffusion layer 8 is formed using boron sound by thermal diffusion and ion implantation on the islands 5-1 and 5-2, and a base layer of a vertical NPN transistor is formed.

(G) Emitter 9-1 of a shibora transistor by N-type diffusion using arsenic or arsenic. I2L element (7
) NPN vertical type) transistor collectors 9-2 and 9-3 are formed. The NPN vertical transistor in the I2L element has a structure in which 5-1 is the emitter, 7-2i is the base, and 9-2 or 9-3 is the collector, which is the reverse of the collector-emitter of a bipolar transistor.

In addition, since the collector all 6 is not necessary in some cases, the collector contact 9-4 of the transistor is formed by an n-type diffusion 9.
and form an emitter contact 9-6 of the I2L element.

( ) 0 After that, contact windows are opened at necessary locations in the silicon oxide film 0 to form aluminum electrodes 11 .

By the way, the propagation delay time of the I2Ii element is given by the time required to charge and discharge the charge accumulated in the I2L element, and in the low current region, the charge accumulated in the junction capacitance of the I2L element becomes dominant and becomes large. In the current range, the charge accumulated in the emitter region of the I2L element becomes dominant, so in order to shorten the propagation delay time in the low current range, it is better to have a low concentration in the epitaxial layer. In order to speed up the propagation delay time in the basin, it is desirable that the epitaxial layer has a high concentration. For this reason, a method has also been adopted in which one layer is diffused into the emitter layer of the I2L element.

However, in addition to increasing the number of steps with this method,
Forming one layer using ion implantation also has the disadvantage that defects are likely to occur.

Purpose of the Invention The present invention aims to improve the above drawbacks by improving the 9WN of the 2L element.
The purpose of this method is to grow a highly doped epitaxial layer directly under the base of a PN) transistor, and continuously grow a lightly doped epitaxial layer thereon to provide a 2L device capable of high-speed operation.

Structure of the Invention In other words, the feature of the present invention is to make the base layer of the vertical NPN transistor of the I2L element deeper than the base layer of the bipolar transistor, and form a highly doped epitaxial layer directly below the base of the vertical NPN transistor. However, by continuously forming a low concentration epitaxial layer thereon, the performance of the IL element is improved.

DESCRIPTION OF THE EMBODIMENTS The present invention will be described below with reference to the step-by-step sectional views of the embodiments shown in FIGS. In FIG. 2, the same symbols are used for the same parts as in FIG. 1.

(People) Using arsenic or antimony on a P-type silicon substrate 1, a "type low resistance buried layer 2" is formed by thermal diffusion or ion implantation.
form.

(2) On the substrate 1, first, a highly doped N-type epitaxial layer 3-1 is formed, and then an epitaxial layer 3-2, which is lower in concentration than 3-1, is formed.

(C) Isolation is achieved by forming a P+ type isolation diffusion layer 4 of boron or the like to a depth that reaches the P type substrate 1 for isolation between transistors, diodes, resistor islands, and isolation from I2L. N-type island 5-1.6-2
form.

(D) In order to make a collector all 6 which is a highly concentrated N-type layer, phosphorus or the like is used to form it so as to reach the n++-containing layer 2 by thermal diffusion or ion implantation.

傳) Next, injector 7-1 of the P-type I2L element is applied to the island 5-1 using poron or the like using thermal diffusion or ion implantation.
and a vertical NPN) transistor pace 7-2. At this time, the P type diffusion layer is made shallower than the epitaxial layer 3-2.

(G) Next, we used boron to the island 6-2 using thermal diffusion, ion implantation, etc. to create a shallower P than the injector of Ryo-1.
A type diffusion layer 8 is created to form the base of a bipolar transistor.

(G) After heating, a t-layer is formed using phosphorus or arsenic by thermal diffusion or ion implantation. This forms the emitter 9-1 of the bipolar transistor and the collector 9-2, 9-3 of the I2L npn vertical transistor.

Also, there are cases where Collector All 6 is not necessary.
The collector contact 9- of the transistor is formed by the type diffusion 9.
4 and an emitter contact 9-5 of the IL element are also formed.

1'M) After the process, contact windows are opened in the silicon oxide film 510210 at necessary locations and electrodes 11 are formed.

According to the above method, it is possible to form a highly doped N-type epitaxial layer directly below the I2L element pace, and then form a lower-doped N-type epitaxial layer on top of it. The propagation delay time of the 2L element can be made faster in the region, and the withstand voltage of the bipolar transistor can also be ensured.

Effects of the Invention According to the present invention, I2
This method realizes a specific method of increasing the propagation delay time of the L element, and it is possible to realize the integrated formation of a high-speed process 2L and a normal bipolar transistor.

[Brief explanation of drawings]

Figures 1 (A) to (6) are cross-sectional views of an I2L element and an NPN transistor in the order of the manufacturing process according to the conventional method, and Figures 2 (A) to (6) are cross-sectional views of an embodiment of the present invention in the order of the manufacturing process. be. 1...p-type Si substrate, 2...n+ type buried layer, 3...n-type epitaxial layer, 3-1.
...High concentration n-type epitaxial layer, 3-2...
...Low concentration n-type epitaxial layer, 4...P
Type separation diffusion layer, 5-1.6-2...n-type layer, 6
・・・・・・N-type collector all, 7-1・・・・・・
・P-type 2L element injector, 7-2...P
Pace of vertical NPN) transistor of type I2L element, 8.
...base of bipolar transistor, 9-1.
...Emitter of bipolar transistor, 9-2
... Collector of IL element, 9-3 ...
Collector of IL element, 9-4.9-5...n
Diffusion layer, 10...Silicon dioxide film, 11...
····electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1 Figure 2

Claims (1)

[Claims] A buried layer of an opposite conductivity type is selectively formed on a semiconductor substrate having one conductivity type, and a high concentration semiconductor layer of the opposite conductivity type is first formed on the substrate, followed by a low concentration semiconductor layer. a step of separating this semiconductor layer to form first and second island regions for forming an I^2L element and a bipolar transistor;
a step of forming an injector of the element and a base layer of the vertical NPN transistor; a step of forming the base of the bipolar transistor in the second island region to be shallower than the injector of the I^2L element; A method for manufacturing a semiconductor device, comprising the steps of simultaneously forming a base of the I^2L element and an emitter of the bipolar transistor on the base of the bipolar transistor, respectively.