GB2146500A - Digital to analog convertor - Google Patents

Abstract

A digital to analog convertor comprises a register (20) for storing a binary digital signal D0-D7 supplied thereto, a counter (10) for counting a clock signal, NAND gates (30) for detecting the coincidence between an output signal of each stage of the counter and an output signal of each digit of the register, and a low pass filter (38) for filtering out an alternating component from an output signal of the NAND gates. Each bit is accordingly effective to gate a certain section of the counter to provide output pulses of equal, corresponding spacing. <IMAGE>

Description

SPECIFICATION Digital to analog convertor This invention concerns a digital to analog convertorforconverting a parallel binary digital signal into an analog signal and, particularly, it relates to a digital to analog convertor which converts a parallel binary digital signal into a pulse-width modulated serial pulse signal and further converts the pulse signal into an analog signal by applying averaging treatment to the thus converted signal.

For the purpose of driving a spindle motor or the like for rotating the magnetic disc of a magnetic disc memory underthe control of a central processing unit, a parallel binary digital signal outputted from the central processing unit is generally converted into an analog signal by way of a digital to analog (D/A) convertor, to thereby control the motor by the thus converted analog signal. However, since the use of a D/A convertor having a resistor ladder circuit and an electronic switch makes the control circuit expensive, it may be considered desirable to simplify the circuit structure and thereby reduce the cost by using a D/A convertor comprising a pulse-width modulator and a low pass filter. Since the spindle motor has a large inertia, control of the rotational number of the motor by a pulse-like voltage or current provides no substantial problem.

However, in a case where the motor to be controlled is used for rotating a magnetic disc or the like, noises are generated upon supply of the pulse-like power and this becomes noticeable particularly when the supplied power is switched at a high speed. Accordingly, it is desirable to reduce the ripple component in the supplied power to an allowable level through the use of a low pass filter in the case of using the D/A convertor comprising a pulse-width modulator and a low pass filter. However, in the conventional D/A convertor of this type, reduction of the ripple component in the output waveform inevitably increases the time constant of the low pass filter making the sizes of the low pass filter components larger and increasing the cost. Also the conversion speed is greatly reduced.

According to the present invention, there is provided a digital to analog convertor comprising a register means for storing a parallel binary digital signal supplied thereto, a binary counter means having a number of stages corresponding to the number of digits in said register means and counting a clock signal supplied thereto, a plurality of first gate means disposed corresponding to each of the digits of said register means, the first gate means corresponding to the first digit of said register means being arranged to detect the coincidence between the output signal from the corresponding first digit of the register means and the first output signal from the corresponding initial stage of the counter means and outputting a pulse signal indicating that coincidence, each of the remaining first gate means being arranged to detect the coincidence between the output signal from corresponding the digit of the register means, the first output signal from the corresponding stage of the counter means and all of the second output signals which corresponds to an inverted signal to the first output signals from the stages preceding said corresponding stage of the counter means and outputting a pulse signal indicating the coincidence, a second gate means for combining serial pulse signals outputted from each of said first gate means, and a filter means for detecting the average value for the amplitude of the serial pulse signal outputted from said second gate means.

The invention also provides a digital to analogue convertor a digital to analog convertor with PWM output comprising a register to be loaded with control data, a counter for counting clock pulses and a decoding circuit for decoding the output signal from the counter based on the output signal from the register, thereby selecting at an equal interval a count section corresponding to each of the bit outputs from the register among each of the count sections within one counting cycle of the counter and outputing a pulse signal which becomes active in the selected count section.

This invention will be further described by way of non-limitative example with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram for a digital to analog convertor of a conventional type; Figure 2 is a timing diagram for the explanation of the operation of the digital to analog convertor illustrated in Figure 1; and Figure 3 is a circuit diagram of one embodiment according to this invention.

In a conventional type D/A convertor 2 comprising a pulse-width modulator 1 illustrated in Figure 1, an n bit counter 3 counts a clock signal 4 supplied thereto, and issues a carry output signal CY to the reset terminal R of a set-reset flip-flop 4 and a count output signal CD composed of n bits for indicating the counted content of the counter 3 to a coincidence detection circuit 5 respectively. A data latch circuit 6 for latching a parallel binary digital signal composed of n bits supplied from a central processing unit CPU latches the data signal at every predetermined interval and supplies the n-bit data signal DIN after latching also to the coincidence detection circu it 5.The coincidence detection circuit 5 compares the signal DIN and the signal CD and supplies a coincidence signal S1 to the set input terminal S of the flip-flop 4 when the two signals are coincide with each other.

In the D/A convertor 2, the output signal S2 of the flip-flop 4 comprises a pulse signal as shown in Figure 2, in which the period To is represented as 2xTc assuming the period of the clock signal + is Tc, and the period TI at the logic level "1" is expressed as (N1 xTo)/2" assuming the value for the signal DIN expressed by the binary number as N1 is in decimal notation. For example, if the counter 3 is a 8 bit counter, the signal DIN is 8 bit parallel digital signal and the clock period Tc is 1 usec, the period To is 256 usec.In this case, if the signal DIN is (01111111), the period T1 is 128 usec and thus the signal S2 is a pulse signal of a 50 % duty ratio, which is supplied to the low pass filter 7 comprising a register and a capacitor. As apparent from the Fourier series for the signal S2, the amplitude of the fundamental frequency signal is largest at the 50% duty ratio and, accordingly, an analog signal containing nearly 50% ripple component in addition to the DC component is output from the filter 7 even if a low pass filter with a 1 KHz cut off frequency is used. In order to further eliminate the ripple component, it is required to use a low pass filter having a lower cut off frequency, that is, with a larger time constant.As the result, the conventional D/A convertor has a drawback in that if it is intended to more fully eliminate the ripple component, the conversion speed is reduced and the low pass filter requires larger component values, increasing the cost.

In a D/A convertor 9 according to this invention illustrated in Figure 3, an asynchronous binary 8 bit counter 10 comprises a serial circuit of D type flip-flops 11 to 18 and cyclically counts a clock signal 4) from 0 to 28-1.A 8 bit control register 20 comprising D type flip-flops 21 to 28 are supplied at the data input terminals DO - D7 thereof with a parallel binary digital control signal from a central processing unit. The control register 20 latches the signal being input and outputs the same at the Q terminals when a data strobe pulse ST is supplied and clears the thus latched signal when a clear pulse CLE is supplied.A decoder 30 comprising AND gates 31 to 36 and NAND gates GOto G8 decodes the counted output from the counter 10 based on the output signal from the control register 20, to thereby output a pulse-width modulated signal.

An output from the gate G8 of the decoder 30 is supplied to the D terminal of a D-type flip-flop 37, and the flip-flop 37 again synchronizes the pulse-width modulated signal from the gate G8 with the signal 4 and supplies the same to a low pass filter 38. That is, the flip-flop 37 serves to eliminate the effect of the gating delay time in each of the section within the decoder 30.

At first, when the clock signal 4 is supplied to the counter 10, the counter 10 repeats counting from 0 to 28-1.Then, when the strobe pulse ST arrives at the control register 20 after the supply of the control data, for example, (00000001) to the D terminals (D7, D6, D5, D4, D2, D1, DO) of the register 20, the Qoutputsignal of the flip-flop 21 is at the level "1 " and all of the Q output signals of the flip-flops 22 to 28 are at the level "0".

As the result, the output signal from each of the NAND gates G1 to G7 is always at the level "1" irrespective of the output signal from the counter 10, while the NAND gate GO turns its output signal to the level "0" (active "0") only when the output signals on the positive logic side, that is, Q output signal (b7, b6, b5, b4, b3, b2, bl, bO) of the flip-flop ii to flip-flop 18 are (01111111). The period for the level "0" coincides with the one cycle period Tc of the clock pulse 4.Further, assuming the period during which the output signal of the counter 10 goes from (00000000) to (1111111) is T (=256 x Tc) and numbering each ofthe sections of T/256 successively as tO - t255, the 0 output signal from the counter 10 takes (01111111) only at the section t1 27.

Accordingly, when (00000001) is loaded into the control register 20, the output of the gate G8 takes the level "1" only at the section tl 27.

In the same manner when (00000010) is loaded into the control register 20, the output signal of the flip-flop 22 takes the level "1" and the output signals from the flip-flops 21,23 - 28 are at the level "0". As the result, the output signals from the gate gO, G2 - G7 are always at the level "1" irrespective of the output signals from the counter 10 and the output signal from the gate G1 takes the level "0" only when the output signal from the counter 10 is (x011 1 1 1) where the bit indicated by x represents a don'scare bit which may be either 0 or 1. The output signal from the gate G1 takes the level "0" at the two sections t63 and t191.

As described above, the value of m and the numbers of the sections tm in which the output signals from the gates GO to G7 are at the level "0" are different depending on which input terminals DO - D7 of the control register 20 is supplied with the input "1". Table shows the relationship between the input terminal DO - D7 to which the level "1" is inputted and the sections in which the signal takes the level "0" (active "O").

It can be seen from the table that "0" level pulse is outputted at an equi-interval of time corresponding to each of the input terminals DO - D7, that is, to each of the bits of the control register inputted with "1".

Further, in case inputs "1" are inputted to a plurality of input terminals, since the logical sum is eventually taken through the NAND gate G8 (Figure 3), the final number of the "0" level pulses is the sum of the active pulse numbers (number of active "0" sections) written in the columns corresponding to each of the input terminals DO - D7 in the table.

As described above, the illustrated D/A convertor since a number of pulses corresponding to the data loaded in the control register are outputted at a substantially equal interval, the time constant of the low pass filter for eliminating the ripple component in the output waveform can be smaller. For instance, the time constant of the low pass filter is about 100 usec when the clock signal + is at 1 MHz, so the components of the low pass filter can be reduced greatly in the size.

As described above, according to this invention, the ripple component in the output signal can be eliminated by using a low pass filter of a small time constant to thereby attaining the miniaturization and cost reduction in the low pass filter. Accordingly, in a case where this invention is applied to the speed control of e.g. a spindle motor in a magnetic disc memory, motor speed can be set rapidly to a control value since the time constant of the low pas filter is small and the noise can be reduced since the ripple component in the speed control signals can be reduced.

TABLE Input Output from the clock counter Interval Number of terminal Enable to be decoded of the ac- sections supplied gate Section tm to be active "0" tive "0" to be acwith "1" b7 b6 b5 b4 b3 b2 bi bO section tire"0" DO GO O 1 1 1 1 1 1 1 m = 127 256 D1 G1 x 0 1 1 1 1 1 1 m = 63,191 128 2 D2 G2 x x 0 1 1 1 1 1 m = 31,95,159,223 64 4 D3 G3 x x x 0 1 1 1 1 m=15, m = 15,47,79,111,143 32 8 175,207,239 D4 G4 x x x x 0 1 1 1 m = 7,23,39,55,71,87, 103,119,135,151,167, 16 16 183,199,215,231,247 D5 G5 x x x x x 0 1 1 m = 3,11, 8P+3,...

(P: integer) , 8 32 243,251 D6 G6 x x x x x x 0 1 m = 1,5,9 ,4P+1, (P: integer) , 4 64 249,253 D7 G7 x x x x x x x O m = 0,2,4, ,2P, P: integer) 252, 2 128 254

Claims (8)

1. A digital to analog convertor comprising a register means for storing a parallel binary digital signal supplied thereto, a binary counter means having a number of stages corresponding to the number of digits in said register means and counting a clock signal supplied thereto, a plurality of first gate means disposed corresponding to each of the digits of said register means, the first gate means corresponding to the first digit of said register means being arranged to detect the coincidence between the output signal from the corresponding first digital of the register means and the first output signal from the corresponding initial stage of the counter means and outputting a pulse signal indicating that coincidence, each of the remaining first gate means being arranged to detect the coincidence between the ouput signal from corresponding the digit of the register means, the first output signal from the corresponding stage of the counter means and all of the second output signals which corresponds to an inverted signal to the first output signals from the stages preceding said corresponding stage of the counter means and outputting a pulse signal indicating the coincidence, a second gate means for combining serial pulse signals outputted from each of said first gate means, and a filter means for detecting the average value for the amplitude of the serial pulse signal outputted from said second gate means.

2. The digital to analog convertor of claim 1, in which each of the first gate means comprise an AND circuit for performing logical product operation for the output signals supplied thereto and the second gate means comprises an OR circuit for performing logical sum operation for the serial pulse signals outputted from the AND circuits.

3. The digital to analog converter of claim 2, in which the OR circuit comprises inversion circuits for inverting the signal outputted from each of the AND circuits and an AND circuit for performing the logical product operation of the signals outputted from each of the inversion circuits.

4. The digital to analog convertor in any one of claims 1 to 3, in which the filter means comprises a low pass filter.

5. The digital to analog convertor in any one of claims 1 to 4, in which the register means comprises eight D-type flip-flops.

6. The digital to analog convertor in any one of claims 1 to 5, in which the counter means comprises eight D-type flip-flops.

7. A digital to analog convertor with PWM output comprising a register to be loaded with control data, a counter for counting clock pulses and a decoding circuit for decoding the output signal from the counter based on the output signal from the register, thereby selecting at an equal interval a count section corresponding to each of the bits outputs from the register among each of the count sections within one counting cycle of the counter and outputing a pulse signal which becomes active in the selected count section.

8. A digital to analogue convertor constructed and arranged to operate substantially as hereinbefore described with reference to and as illustrated in Figure 3 of the accompanying drawings.