DE3431612A1 - DIGITAL / ANALOG CONVERTER - Google Patents

Description

The invention relates to a digital / analog converter (D / A converter) for converting a parallel supplied binary digital signal into an analog signal, in particular to a D / A converter, which is a parallel binary digital signal into a pulse width modulated serial pulse signal and this pulse signal into an analog signal by applying averaging to the converted one Signal converts.

Turntable drives or the like for magnetic disks of a magnetic disk storage are with the help of a central control unit controlled. For this purpose, a parallel binary digital signal is sent from the central control unit usually with the help of a D / A converter into a

15 converted to analog signal, with the motor then going through

the converted analog signal is controlled. However, since the use of a D / A converter with a resistor network and electronic switches make the control circuit more expensive, it would be desirable to change the circuit structure to simplify and reduce the cost of doing so by a D / A converter with a pulse width modulator and a low pass filter is used. As the turntable drive has a high inertia, the control of the rotational speed of the motor is pulse-like Basically, voltages or currents are problem-free. But where the zxi controlling drive motor for driving a Magnetic disk or the like is used, interference and during the pulse-like energy supply Generated noise signals, in particular when the supplied energy is supplied with a high switching frequency. Accordingly, it is necessary to reduce the ripple component in the supplied energy signal to a permissible level with the help of a low-pass filter if a D / A converter with pulse width modulator and low-pass filter is used. In conventional D / A converters of this type, however, the reduction inevitably increases Ripple component in the output signal, the time constant of the low-pass filter, so that the essential structural

elements for this low-pass filter must be designed larger, which increases the costs accordingly. In addition, there arises a problem that the converter speed is extremely lowered.
5

The invention is based on the object of specifying a D / A converter with which an analog output signal is emitted whose ripple component is reduced to a low level, even when using a low-pass filter: with a small time constant, thereby reducing the size and manufacturing costs as well high speed conversion can be achieved.

This object is according to the invention by the characterizing Part of claim 1 specified features solved.

Accordingly, a D / A converter with a pulse width modulated Output signal on a register that is loaded with control data, and also a counter for counting Clock pulses and a decoder circuit that converts the output of the counter on the basis of the output signal of the register is decoded, in each case at the same time intervals a counting section corresponding to each bit output of the register out of all of the counting sections is selected within a counting cycle of the counter and a pulse signal is output that during the selected Counting section becomes active.

A digital / analog converter according to the invention is characterized in that it has a register for storing a having binary digital signals fed in parallel, furthermore a binary counter with counting stages corresponding to the Number of digits in the memory for counting a supplied clock signal, several first gate circuits for each digit of the register, the first gate circuit that is assigned to the first digit of the register being coincidence

between the output signal of the first digit of the register and a first output signal of the assigned input stage of the counter and emits a pulse output signal indicating this coincidence and the remaining first gate circuits coincidence between the output signal of the corresponding point of the register, determines the first output signal of the assigned counting stage of the counter and a second output signal, each of which corresponds to the inverted first output signals of those counting stages that of the assigned counting stage of the counter precedes, and then emits a pulse output signal indicating this coincidence, and that the digital / analog converter further comprises second gate circuits for adding serial pulse signals, the have been delivered by each of the first gates, and that a filter is also provided in order to obtain an average value the amplitude of the serial, from the second gate circuits to form output signal output.

Further refinements of the invention emerge from the subclaims out »

The invention is based on one embodiment Drawing explained in more detail. In the drawing show:

Figure 1 is a block diagram of a conventional one Digital / analog converter;

Figure 2 is a timing diagram to explain the functioning of the digital /

Analog converter;

FIG. 3 shows a circuit diagram for a digital / analog converter according to the invention.

In a conventional digital / analog (D / A) converter 2 according to Figure 1 with a pulse width modulator 1, an n-bit counter 3 counts a clock signal φ fed to it and outputs an overflow signal CY to the reset connection R of a resettable and resettable flip Flops 4 (SR flip-flop) and a counter output signal CD composed of n-bits and indicating the content of counter 3 to a coincidence detector circuit 5. A latching circuit 6 for holding a binary digital signal composed of η bits and supplied from a central control unit CPU holds the data signal every predetermined clock and then also supplies the n-bit data signal DIN to the coincidence detector circuit 5. The coincidence detector circuit compares the signals DIN and CD and delivers a coincidence signal S1 to the set input S of the flip-flop 4 when the two signals coincide.

In this D / A converter 2, the output signal S2 is the

Flip-flop 4, a pulse signal corresponding to Figure 2, the period To is represented by 2 xTc when the period of the clock signal φ is referred to as Tc. The period T1 at the level "1" can be expressed as (NIxTo) 2 ⁿ , the value for the signal DIN being expressed by the binary number Nl in decimal notation. If z. B. the counter 3 is an 8-bit counter, then the signal DIN is a parallel digital 8-bit signal. In addition, if the clock period Tc is one microsecond, then the period To is 256 \ isec. If in this case the signal DIN is the signal (01111111), the period T1 is 128 μεβο, so that the signal S2 is a pulse signal with a width corresponding to half the period To. This signal is fed to a low-pass filter 7 with a resistor and a capacitor. As can be seen from the Fourier decomposition of the signal S2, the amplitude of the signal component with the fundamental frequency is greatest at the mentioned 50% pulse width ratio. Accordingly, an analog signal is emitted at the output of the filter 7, which

almost 50% ripple component in addition to the direct current component even when a low-pass filter with a cutoff frequency of 1 kHz is used. In order to further reduce the ripple component, it is necessary to use a low-pass filter with an even lower one To use cutoff frequency, d. i.e. a filter with a correspondingly higher time constant. A conventional one D / A converter in which the ripple component in this Sense is to be reduced has the disadvantage that the conversion time is reduced accordingly and that the The low-pass filter must be designed to be correspondingly larger, thereby increasing the cost.

In a D / A converter 9 according to the invention, which is shown in Figure, an asynchronous binary 8-bit counter 10 a series circuit of D flip-flops 11 to 18 on and

cyclically counts a clock signal φ from 0 to 2 -1. An 8-bit control register 20 with D flip-flops 21 to 28 is supplied with a parallel binary digital control signal from a central control unit at the data input connections DO to D7. The control register 20 holds the indicated signal and passes it on to the Q terminals when a data strobe pulse ST is applied. The held signal is cleared when a clearing pulse CLE is applied. A decoder 30 with AND gates 31 to 36 and NAND gates GO to G8 decodes the counter output of the counter 10 on the basis of the output signal of the control register 20 and emits a pulse-width-modulated signal at the output. An output signal of the NAND gate G8 of the decoder 30 is fed to the D terminal of a dynamic D ^ flip-flop 37. The flip-flop 37 synchronizes the pulse-width-modulated signal from the gate G8 with the signal φ and feeds this to a low-pass filter 38. The flip-flop 37 therefore serves to eliminate the effect of the delay time of the gate circuit in each section within the decoder 30.

The functionality of the described D / A converter is the following:

When the clock signal 4 is first supplied to the counter 10 / counts the counter 10 cyclically from 0 to 2 ⁸ -1. When the strobe pulse ST arrives at the control register 20 after control data, e.g. B. the signal (00000001) the D connections (D7, D6, D5 _f D4, D3, D2, D1, DO) of the register 20 have been fed, then the output signal of the flip

Flops 21 at the Q output have the level "1%" while all other Q output signals of the flip-flops 22 to 28 have the level "0". Accordingly, the output signals of all NAND gates G1 to G7 are at the level "1" _r and independently of the output signal of the counter 10, whereas the NAND gate GO emits an output signal with the level "0" (active "0") only when the output signals on the positive logic side, i.e. the Q output signals (b7, b6, b5, b4, b3, b2, b1, b0) of the flip-flops 11 to 18 signals (01111111)

²⁰ are. The period for level "0" coincides with a

Cycle period Tc of the clock pulse φ together. If it is assumed that the time during which the output of the counter transitions from the signal (00000000) to (11111111), T is 256 χ Tc, and if all sections

corresponding to 'T / 256 are successively counted as tO to t255, then the counter's Q output takes the value (01111111) only in section t127. If so the signal (00000001) is input to the control register 20, then takes the output of the NAND gate G8

³⁰ the level "1" only during the section t127.

If the signal (00000010) is input into the control register 20, the output signal is correspondingly increased of the flip-flop 22 Oen level "1", while the output signals of the flip-flops 21 and 23 to 28 are at "0" level. Accordingly, the output signals of the gates GO and G2 to G7 are always at the level "1" regardless of the output signals of the counter 10,

while the output signal of the gate G1 ^{only shows the level value 11} O "if the output signal of the counter 10 is a signal (xOI11111), the bit labeled χ being any bit with the value 0 or 1. The output signal of the gate G1 has the level "0" in the two sections T63 and T191.

As described above, the value of m and the numbers of the sections tm in which the output signals of the gates GO to G7 are at the "0" level are different depending on which input terminals DO to D7 of the control register 20 an input signal with the level "1" is supplied. The table shows the relationship between the input terminals DO to D7, to which an input signal of the "1" level is supplied, and the periods in which the output signal ^{assumes the level 11} O "(active" 0 ").

20 25 30 35

to
cn

-fco
O

cn

cn

TABEL

Signal "1" release
gate π:
output to be decoded
of the cycle counter Time segment tm with active "O" Interval de
Section
with active
HQlI number of
Time segment
te with acti
ver "0" DO GO b7 b6 b5 b4 b3 b2 bl bO m = 127 256 1 Dl Eq 01111111 m = 63.191 128 2 D2 G2 xOllllll m = 31, 95, 159, 223 64. 4th d3 G3 χ χ O 1 1 1 1 1 m = 15, 47, 79, 111, 143,
175, 207, 239 32 8th D4 G4 xxxOllll m = 7, 23, 39, 55, 71, 87,
103, 119, 135, 151, 167,
183, 199, 215, 231, 247 16 16 D5 G5 xxxxOlll m = 3, 11, ..., 8P + 3, ...
243, 251 8th 32 D6 G6 xxxxxOll m = 1, 5, 9 ...., 4P + 1,
(P: integer),.
249, 253 4th 6 4 D7
• I G7 XXX XXX Ol 254 2 12 8 xxxxxxxO

CO, CO

From this table it can be seen that pulses with the level "0" in equal time intervals corresponding to the Pulses are delivered to the input terminals DO to D7, d. H. according to the positions in the tax register, · to which an input signal "1" is applied. Furthermore, since the logical sum through the NAND gate G8 {Figure 3) is formed in the case that input signals with the level "1" are fed to several input connections, the result number of the pulses with the level "0" the sum of the number of active pulses (number of time segments with active "0") according to the columns in the table for the individual input connections DO to D7.

In a D / A converter according to the invention, since a number of pulses corresponding to the data entered in the control register are output as output signals at equal time intervals, the time constant of the low-pass filter for suppressing the ripple component in the output waveform can also be made smaller. So is z. B. the time constant of the .Tiefpassfilters about 100 nsec when the frequency of the clock signal φ 1 fflz, whereby the determining elements of the lowpass filter can be significantly reduced in size.

As described above, according to the invention, the waviness fraction in the output signal with the help of a Low-pass filter with a small time constant can be eliminated, whereby this low-pass filter is miniaturized and can be produced cheaper. If z. B. a D / A converter according to the invention for speed control a turntable motor is used for a magnetic storage disk, the motor speed can increase quickly can be set to a desired value because the time constant of the low-pass filter is small. Also can the noise can be reduced, since the ripple component in the speed control signals is reduced can.

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Claims (7)

Claims Digital / analog converter with pulse width modulator and low-pass filter, characterized in that the digital / analog converter (9) has a register (20) for storing a binary digital signal fed in parallel, also a binary counter (10) with counting levels corresponding to the number of digits in the memory (20) for counting a supplied clock signal, several first gate circuits (GO to G7, 31 to 36) for each digit of the register (20), the first gate circuit (G7) that is assigned to the first digit of the register (20) is, coicidence between the output signal of the first digit (D7) of the register (20) and a first Output signal of the assigned input stage (11) of the counter (10) determines and this coincidence emits indicating pulse output signal and the remaining first gate circuits coincidence respectively between the output signal of the corresponding point of the register (20), the first output signal of the associated Level of the counter (10) and a second output signal, each of which is the inverted first output signals of those counting stages speaks, which precede the assigned counting stage of the counter (10), and then this coincidence emits indicating pulse output signal, and .that the digital / analog converter (9) also has second gate circuits (G8, 37) for adding serial pulse signals which have been delivered by each of the first gates, and that further a Filter (38) is provided to take an average of the amplitude of the serial, from the second gate circuits to form output signal output. 2. Digital / analog converter according to claim 1, characterized in that each first gate circuit has an AND gate (31-36) for forming a logical product from the supplied output signals, and that the second gate circuits (G8, 37) an OR circuit for forming a logical sum for the AND gates have serially output pulse signals. 3. Digital / analog converter according to claim 2, characterized in that that the OR circuit inverter for inverting the output signals from the AND gates and an AND gate for forming a logical product of the output signals emitted by the inverters having. 4. Digital / analog converter according to one of the preceding Claims, characterized in that the filter contains a low-pass filter (38). 5. Digital / analog converter according to one of claims 1 to 3, characterized in that the register (20) is eight D flip-flops (21 to 28). 6. Digital / analog converter according to one of claims 1 to 3, characterized in that the counter (10) has eight D flip-flops (11 to 18). 7. Digital / analog converter with pulse width modulated output signal, characterized in that the digital / analog converter (9) has a register (20) with Control data is loaded, furthermore a counter (10) for counting clock pulses and a decoding circuit (30), which decodes the output signal of the counter (10) on the basis of the output signal of the register (20), a time segment corresponding to each bit output of the register (20) below at regular intervals all time segments within a counting cycle of the counter (10) is selected and a pulse signal is emitted which becomes active during the selected counting section.