SU1354244A1 - Indicating device - Google Patents

Abstract

The invention relates to automation and computing. It can be used in information display devices with dynamic indication. The aim of the invention is to improve the quality of the display of information by increasing the brightness; In order to achieve this goal in the SP 00 ate

Description

a device containing a generator; pulses 1, counter 2, first 3 and second 6 decoders, first element AND 9, element AND-HE 7, keys 4, seven-segment indicators 5, binary tetrads 10 and multiplexers 8, enter 1

The invention relates to automation and computing and can be used in the construction of the device. Control of digital information.

The purpose of the invention is to improve the quality of displaying information due to brightness enhancement.

The drawing shows a diagram of the device for display.

The display device comprises a series-connected pulse generator 1, a counter 2 and the first decoder 3, keys 4, the outputs of which are connected to the control inputs of the indicators 5, the information inputs of which are connected to the outputs of the second decoder 6, the last output of which is connected to the first input of the first element AND-7, switches 8, equaling inputs of which are connected to the outputs of the bits of counter 2 and the inputs of the first element 9, the output of which is connected to the input of the last key 4, binary tetrads 10, the outputs of which are device information are input (switch 8), the third 11 and second 12 AND gates, the chain of series-connected capacitor 13 and resistor 14 connected to the first power supply circuit 15 and the second flip-flops 16, second 17 and first 18 elements are not.

The display device operates as follows.

The pulses from the generator 1 pulses arrive at the counter 2, the conversion factor of which is equal to the number of indicators 5 (in this case 8)

The state of the outputs of counter 2 changes with the arrival of each pulse. The code of the three bits of counter 2 is fed to the information inputs of the three-bit first decoder 3, to the inputs of the first element I 9 and to the control inputs of the eight-input commune first 18 and second 17 elements NOT, second 12 and third 11 elements And, first 15 and second 16 triggers that ensure the increase in the pulse duty cycle at the output of the first decoder. 1 il.

0

15

In accordance with the code at the outputs of the counter 2, the outputs of the switches 8 appear signals corresponding to the values of the individual bits of the counting tetrads 10. Thus, when the code value of the 000 counter 2 appears at the outputs of the switches 8, the binary equivalent of the first ) the decimal digit of the number, with the code 001 of the counter 2 - the second one, etc., with the code 111 - the eighth (younger) digit. The seven-segment second decoder 6 converts the four-digit code from the outputs of switches 8 into a seven-digit indicator control code 5. The three-input first decoder 3 with a zero signal at the prohibition input is in the locked state - 0 SRI, and with a single signal connects the anode of one of the indicators 5 to the source power supply E, and code combination 000 at the inputs of the first decoder 3 corresponds to the inclusion of the first of the keys 4, code 001 - the second, etc. The inclusion of the last (eighth) display element through the corresponding key 4 is performed by the first element AND 9 with the code combination 111 of the counter 2.

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When the power is turned on by a pulse formed by a circuit of a series-connected capacitor 13 and a resistor 14 connected to the control input of the device, the first trigger 15 is set to one, which leads to the presence of a zero signal at the prohibition input of the first decoder 3, and to the suppression of indicators 5 for all bits except the younger. The first trigger 15 is in a single state until a single signal appears at the output of the first element 9, setting the first trigger 15 to the zero state

At the same time, with a single signal from the output of the first element AND 9, the second trigger 16 is set to one, because the S input has a logical one signal and the R input from the output of the first HE 18 the third element And 11 receives a logical zero signal, which leads to the invariance of the zero signal at the prohibition input of the first decoder 3, locking the first decoder 3 and the keys 4 of all bits except the younger one, and disconnecting from the power source Corresponding indicators 5. A single signal from the output of the first element And 9 opens the key 4, which includes the last indicator 5, indicating the state of the outputs of the seven-segment second decoder b, which decodes the output signals of the switches 8.

With the arrival of a pulse, counter 2 is set to the zero state. If the high bits of the displayed number are zero, then the zeros are present at the inputs of the second seven-segment decoder 6. At the first six outputs of the second decoder 6 (AF), the seventh output appears (G) - a single signal. A single signal at the seventh output (G) is also present on the presence of 6 code combinations 0001 and 0111 at the inputs of the second decoder.

Therefore, to determine the zero code combinations of binary tetrads 10, the second element HE 17 and Q element NAND 7 are used, the output of the latter with zero code combinations of binary tetrads 10 is a logical zero signal. The second trigger 16 does not change the single state (at the R input, the logical zero signal), the first decoder 3 is locked, and the indicators 5 except the younger one are disabled. The first nonzero state on

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the inputs of the second decoder 6 leads for the information inputs of the logical unit signal, the outputs of the switches of the terminals of the IS-7 element, which at the time of the absence of a signal of the logical unit at the output of the first terminal to the inputs of the second decoder, characterized by the fact that, in order to improve the quality of the display

And 9, entering the R-input of the second information due to the increase in brightness,

The first and second elements are NOT entered into it, the second and third elements are AND, the first and second triggers, the inverse outputs of which are connected to

the first trigger 16 sets it to the zero state. This removes the prohibition of the first decoder 3, opens the corresponding O

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key 4, the corresponding indicator 5 is turned on.

Since the second trigger 16 changes its state to one only at the moment when the last (youngest) indicator 5 is turned on (the presence of a logical unit signal at the output of the first element 9), then the keys 4 are sequentially opened and all subsequent indicators 5 are turned on.

If the displayed number is zero

0

five

0

five

Q

five

the last indicator 5, since the last key is controlled independently of the first decoder 3 by the first element 9, at the output of which one appears at the code combination 111 of counter 2.

Thus, the introduction of the second 17 and first 18 elements HE, the second 12 and third 11 elements And, the circuit of a series-connected capacitor 13 and a resistor 14 connected to the power circuit, the first 15 and second. The 16 triggers provide an increase in the duty cycle of the pulses at the output of the first decoder 3, which leads to an increase in the brightness of the displayed information, thereby improving the quality of the display.

Claims (1)

Invention Formula A display device containing serially connected pulse generator, a counter whose outputs are connected to control inputs of switches, inputs of the first AND element and information inputs of the first decoder, outputs of which are connected to information inputs of keys, control inputs of which are connected to the power bus, outputs of keys connected to the control inputs of the indicators, whose information inputs are connected to the outputs of the second decoder, the last output of which is p. is connected to the first input of the NAND element, the information inputs of the switches are the information inputs of the device, the outputs of the switches are connected to the inputs of the second decoder, characterized in that, in order to improve the quality of the display 5,135,4244. 6. the inputs of the second element AND, output-NOT, and the output - to the input of the installation Which is connected to the control of the second trigger, the second input the input of the first decoder, the output of the pen-element AND is NOT connected to the output element is connected to the input of the second element, the input of which synchronization of the first trigger, to the input-connected to the input of the younger discharge do installation 1 of the second trigger and the second decoder, information the input of the first element is NOT, the output to the input of the first trigger is connected with This is connected to the first input of the zero potential bus, and the input the third element And, the second input of the co-IQ installation in 1 is the control This is connected to the output by an element input device.