GB1600087A

GB1600087A - Multiband radio receiver

Info

Publication number: GB1600087A
Application number: GB2484478A
Authority: GB
Original assignee: Pioneer Electronic Corp
Current assignee: Pioneer Corp
Priority date: 1977-06-03
Filing date: 1978-05-31
Publication date: 1981-10-14
Also published as: JPS54810A; JPS5549462B2; DE2824345A1

Description

(54) MULTIBAND RADIO RECEIVER (71) We, PIONEER ELECTRONIC CORPO- RATION, a Japanese Company of No. 4-1 Meguro l-Chome, Meguro-Ku, Tokyo, Japan, do hereby declare the invention for which we pray that a Patent may be granted to us and the method by which it is to be performed to be particularly described in and by the following statement :~ This invention relates to a multiband radio receiver in which both bands and channels can be digitally preset, and particularly to an improvement in a digital-toanalog convertor included in an electronic tuning system for such a receiver.

Recently, due to the rapid progress of electronic engineering, a variety of radio receivers have been proposed. For example, a digitally controlled preset radio receiver was disclosed in applicant's Japenese Utility Model Publication No. 93607/1976. In the above conventional radio receiver, the channel preset system comprises a preset switch; a channel selecting switch; a pulse generator for selectively generating up pulses and down pulses; an UP/DO;WN counter connected to the pulse generator; a digital display means for displaying a frequency value in response to the digital output signal of the U/D counter; a digitalto-analog convertor connected to the U/B counter to convert the digital output signal thereof into an analog signal, the analog signal being applied to varactor diodes in a tuning circuit; a memory means such as a random access memory (RAM) for memorizing the output of the U/D counter and providing outputs as to the data addressed therein to the U/D counter, and a control circuit for controlling write and read-out operation of the-RAM. Furthermore, as to the D-A convertor, although a variety of the D-A convertors have been proposed and a variety of integrated circuits which constitute the D-A convertor have been also proposed, it is impossible to provide most of them with a number of input and output terminals. Therefore, the conventional D-A convertor which comprises a pulse synthesizer and a low pass filter is usually employed. Such a synthesizer is described in USP 3,603,977.

The above mentioned pulse synthesizer provides a serial pulse train including a predetermined number of pulses corresponding to the output of the U/D counter by selecting output signals of respective stages of the counter, which are obtained by frequency dividing the output of the pulse generator according to the output of the U/B counter in a parallel mode, and synthesizing them into a rectangular wave. The serial pulse train is then supplied to the low pass filter in order to obtain a D.C. voltage to be applied to the varactor diodes in the tuning circuit.More clearly, the serial pulse is obtained in a well known manner by providing frequency divided pulse generator signals at various stages of a binary counter within the synthesizer, combining these in AND gates with respective output stages of the U/D counter and then combining the AND gate outputs in an OR gate to achieve the serial pulse train. A more detailed description of the synthesizer operation can be obtained by referring to USP 3,603,977, the disclosure of which is fully and completely incorporated herein by reference.

Briefly, as shown in Figs. 1 and 2, the pulse generator output, in addition to being supplied to the U/D counter 100, is supplied to a binary counter, or commutator 120 comprising four serially connected flip-flops.

The Q outputs of each flip-flop provide successive frequency divisions of the pulse generator signal as shown in Fig. 2. These are combined in AND gates as shown with their Q outputs and the outputs of each stage in the U/D counter to result in the pulse trains shown in parts F-J of Fig. 2 which are then combined in OR gate 220 to form the synthesized pulse train. For the case illustrated in Fig. 2, the U/D counter is full and, therefore, the output of OR gate t2 is a very long high level signal.

In this system, however, the output wave form of the pulse synthesizer is liable to include a chattering noise as shown in Fig.

4 (b) due to transient delay on selectively synthesizing the outputs of the U/D counter and the oscillator. This is mainly to the large number of components in the synthesizer and the switching time required for zilch wch of them to change in succession. This chattering causes the duration of the serial pulse train to be varied, as a result of which 1he D.C. voltage to be applied to the varactor diodes also varies. Accordingly, it is impossible to achieve an accurate and stable tuning operation.

Accordingly, a primary object of the present invention is to improve the conventional radio receiver with an electronic preset tuning system so that an accurate and stable tuning operation is carried out.

Another object of the present invention is to improve the conventional radio receiver with an electronic preset tuning system so that it is possible to provide a suitable and desired output of a digital-toanalog convertor to the varactor diodes included in a tuning circuit.

The foregoing object of the present invention is achieved by supplying the output of a pulse synthesizer through a flip-flop circuit to a low pass filter which constitutes a digital-to-analog convertor together with an oscillator, the pulse synthesizer and the flip-flop circuit.

In the Drawings, Fig. 1 is a block diagram of a conventional D/A convertor; Fig. 2 includes waveforms illustrating the operation of the circuitry of Fig. 1; Fig. 3 is a block diagram illustrating one example of an electronic preset tuning system of a multiband radio receiver according to the present invention, Fig. 4 (a) shows one example of a waveform of an output of an oscillator; Fig. 4 (b) shows one example of a waveform of an output of a pulse synthesizer; and Fig. 4 (c) shows one example of a waveform of an output of a D-type flip-flop circuit.

In Fig. 3 which is a block diagram showing essential components of an electronic preset tuning system according to the present invention, a pulse generator 1 has a pair of output terminals from which a series of either up pulses U or down pulses D and clock pulses KC are selectively generated by manual operation. The output terminals of the pulse generator 1 are connected to a binary UP/BOWN counter 2 which employs the up/down pulses U/D outputted from the pulse generator 1 as a count control signal to count the clock pulses KC applied thereto. An output of the U/D counter 2 is fed to a frequency digital display unit 3. The display unit 3 employs a few most significant bits of the count output of the U/D counter 2 as its input to carry out digital display of the selected frequency.The output of the U/D counter 2 is also fed to an input of a pulse synthesizer 4 which provides a serial pulse train having a number of pulses corresponding to the output of the U/D counter 2 by substantially the same method as described with reference to Figs. 1 and 2. An output of the pulse synthesizer 4 is fed to a D-type flip-flop circuit 6 as a data input and the D;type flip-flop circuit 6 also receives an output of the oscillator 5 as a clock input.

An output of the D-type flip-flop circuit 6 is fed to a low pass filter 7 which constitutes a digital-to-analog (D-A) convertor together with the oscillator 5, the pulse synthesizer 4 and the D-type flip-flop circuit 6. A band selecting switch 8 operates to selectively supply the D.C. output of the low pass filter 7 to a tuning circuit (not shown) to thereby select a desired band, and has stationary contacts a through c corresponding to bands A through C, respectively.

There is provided another band selecting switch 10 having stationary contacts a through c corresponding to bands A through C, which operates in association with the aforementioned band selecting switch 8. A channel selecting switch 9 comprises a plurality of non-lock type switches 9a to 9e and one side of the channel selecting switches 9 are commonly connected. A random access read-write memory (RAM) 11 has a plurality of inputs connected to the output sides of the channel selecting switches 9a through 9e and the stationary contacts a to c of the band selecting switch 10, respectively, in order to memorize the output of the U/D counter 2 at an address assigned by the indications of the channel selecting switches 9a to 9e and the band selecting switch 10, or to read-out the data memorized at an assigned address to supply it to the U/D counter 2.A control circuit 12 has an input connected to a one side of a preset switch 13 the other side of which is connected to a common connection line of the channel selecting switches 9a to 9e and the band selecting switch 10. The control circuit 12 also has inputs connected respective output sides of the channel selecting switches 9a to 9e and the band selecting switch 10. When the preset switch 13 is in an "off" state and any one output from the channel selecting switches 9a to 9e and any one output from the band selecting switch 10 are provided, the control circuit 12 supplies a load signal L to the U/D counter 2. On the contrary, in the case when the preset switch 13 is in an "on" state, it supplies a write signal W to the random access read-write memory 11.

In the thus organized radio receiver with the electronic preset tuning device, if the pulse generator 1 is operated, that is, if the knob of the pulse generator 1 is rotated to generate an up pulse U, for instance, the up pulse U is supplied to the U/D counter 2, and accordingly this causes it to up-count the clock pulses KC from the pulse gene rator 1 successively. The parallel count outputs of the U/D counter 2 are applied to the pulse synthesizer 4, where the signals obtained by subjecting the oscillation signal produced by the oscillator 5 to frequency division, are selectively combined with the corresponding outputs of the U/D counter 2 into a serial pulse train having a number of pulses corresponding to that of the output of the U/D counter 2 in the manner described above.The thus obtained output of the synthesizer 4 is applied to the data input D of D-type flip-flop circuit 6. In this case, assuming that the output of the pulse synthesizer 4, which has a waveform including a chattering noise as shown in Fig. 4 (b), is applied to the data input B with the oscillator 5 generating the output having a waveform as shown in Fig. 4 (a), since the D-type flip-flop circuit 6 operates to receive its input signal when on positive clock pulses, the set output Q which corresponds to the input data signal and from which the undesirable chattering noise included in the input data signal is eliminated can be obtained as shown in Fig. 4 (c). This is because, due to the delay in the synthesizer, the flip-flop is clocked immediately before the chattering begins as can be seen by comparing Figs. 4 (a) and 4 (b).The set output Q of the flip-flop circuit 6 is fed to a low pass filter 7 to remove a high frequency component as a result of which a D.C. voltage signal corresponding to the output of the U/D counter 2 can be obtained. This D.C. voltage signal is applied to a varactor diode included in a tuning circuit (not shown) which is selected by an operation of the band selecting switch 8 so that the corresponding frequency tuning in that band is carried out. On the other hand, the most significant bits of the output of the U/D counter 2 are applied to the digital frequency display unit 3, where the frequency being received is digitally displayed. Disclosed above is the electronic tuning operation in the case where a station is manually selected.

In preset operation, under an assumption that a desired channel in a desired band has been selected in the manual manner described above, the preset switch 13 is turned-on, and then one of the channel selecting switches 9a to 9e corresponding to a channel to be preset is turned-on. As a result, the write signal W is applied from the control circuit 12 to the random access read-write memory 11, so that the count output of the U/D counter 2, that is, a digital signal representative of the tuned frequency can be memorized at an address which is assigned by the band selecting switch 10 of the read-write memory 11 and the channel selecting switch 9a to 9e that has been turned on. Similarly as in the above described case, it is possible to preset desired frequencies for the other channels.

In the case of carrying out the present station selection, an address where a digital signal corresponding to a desired station is memorized is selected by selectively operating the band selecting switch 10 and the channel selecting switches 9a to 9e. In this case, since the preset switch 13 is normally in an "off" state, the load signal L is supplied from the control circuit 12 to the U/B counter 2. As a result, the read-write memory 11 reads, as an adrdess, the outputs of the band selecting switch 10 and any one of the channel selecting switches 9a to 9e which is turned on. The stored signal of the read-write memory 11 is inputted, in a parallel mode, into the U/D counter 2.The output of the U/D counter 2 is applied to the pulse synthesizer 4, whereafter the station selecting operation identical to that in the manual operation is carried out. Thereafter, the preset station selection in the same band can be changed merely by selectively turning on the channel selecting switches 9a to 9e. In addition, in the case where the band should be changed, the preset station selection is carried out by switching the band selecting switch 10 and then selectively turning on the channel selecting switches 9a to 9e.

As is apparent from the above description, in the radio receiver with the electronic preset tuning device according to the present invention, the output of the pulse synthesizer is supplied through the D-type flip-flop circuit to the low pass filter. Therefore, the btype flip-flop circuit accurately and completely eliminates the chattering noise which is included in the waveform of the output signal of the pulse synthesizer.

Accordingly, the variation of the D.C. voltage signal which is applied from the low pass filter to a varactor diode included in the tuning circuit is positively eliminated so as to obtain a stable and positive station selection.

Our co-pending U.K. Patent Application No. 24575/78 describes a receiver having many features in common with that described herein.

WHAT WE CLAIM IS:- 1. A multiband radio receiver having a digitally controlled preset tuning system, in which digital signals for a band and a channel selection are supplied to an up/ down counter having a plurality of stages providing outputs to a digital-to-analog convertor so as to obtain a D.C. voltage signal corresponding to said digital signals,

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. generate an up pulse U, for instance, the up pulse U is supplied to the U/D counter 2, and accordingly this causes it to up-count the clock pulses KC from the pulse gene rator 1 successively. The parallel count outputs of the U/D counter 2 are applied to the pulse synthesizer 4, where the signals obtained by subjecting the oscillation signal produced by the oscillator 5 to frequency division, are selectively combined with the corresponding outputs of the U/D counter 2 into a serial pulse train having a number of pulses corresponding to that of the output of the U/D counter 2 in the manner described above. The thus obtained output of the synthesizer 4 is applied to the data input D of D-type flip-flop circuit 6.In this case, assuming that the output of the pulse synthesizer 4, which has a waveform including a chattering noise as shown in Fig. 4 (b), is applied to the data input B with the oscillator 5 generating the output having a waveform as shown in Fig. 4 (a), since the D-type flip-flop circuit 6 operates to receive its input signal when on positive clock pulses, the set output Q which corresponds to the input data signal and from which the undesirable chattering noise included in the input data signal is eliminated can be obtained as shown in Fig. 4 (c). This is because, due to the delay in the synthesizer, the flip-flop is clocked immediately before the chattering begins as can be seen by comparing Figs. 4 (a) and 4 (b).The set output Q of the flip-flop circuit 6 is fed to a low pass filter 7 to remove a high frequency component as a result of which a D.C. voltage signal corresponding to the output of the U/D counter 2 can be obtained. This D.C. voltage signal is applied to a varactor diode included in a tuning circuit (not shown) which is selected by an operation of the band selecting switch 8 so that the corresponding frequency tuning in that band is carried out. On the other hand, the most significant bits of the output of the U/D counter 2 are applied to the digital frequency display unit 3, where the frequency being received is digitally displayed. Disclosed above is the electronic tuning operation in the case where a station is manually selected. In preset operation, under an assumption that a desired channel in a desired band has been selected in the manual manner described above, the preset switch 13 is turned-on, and then one of the channel selecting switches 9a to 9e corresponding to a channel to be preset is turned-on. As a result, the write signal W is applied from the control circuit 12 to the random access read-write memory 11, so that the count output of the U/D counter 2, that is, a digital signal representative of the tuned frequency can be memorized at an address which is assigned by the band selecting switch 10 of the read-write memory 11 and the channel selecting switch 9a to 9e that has been turned on. Similarly as in the above described case, it is possible to preset desired frequencies for the other channels. In the case of carrying out the present station selection, an address where a digital signal corresponding to a desired station is memorized is selected by selectively operating the band selecting switch 10 and the channel selecting switches 9a to 9e. In this case, since the preset switch 13 is normally in an "off" state, the load signal L is supplied from the control circuit 12 to the U/B counter 2. As a result, the read-write memory 11 reads, as an adrdess, the outputs of the band selecting switch 10 and any one of the channel selecting switches 9a to 9e which is turned on. The stored signal of the read-write memory 11 is inputted, in a parallel mode, into the U/D counter 2.The output of the U/D counter 2 is applied to the pulse synthesizer 4, whereafter the station selecting operation identical to that in the manual operation is carried out. Thereafter, the preset station selection in the same band can be changed merely by selectively turning on the channel selecting switches 9a to 9e. In addition, in the case where the band should be changed, the preset station selection is carried out by switching the band selecting switch 10 and then selectively turning on the channel selecting switches 9a to 9e. As is apparent from the above description, in the radio receiver with the electronic preset tuning device according to the present invention, the output of the pulse synthesizer is supplied through the D-type flip-flop circuit to the low pass filter. Therefore, the btype flip-flop circuit accurately and completely eliminates the chattering noise which is included in the waveform of the output signal of the pulse synthesizer. Accordingly, the variation of the D.C. voltage signal which is applied from the low pass filter to a varactor diode included in the tuning circuit is positively eliminated so as to obtain a stable and positive station selection. Our co-pending U.K. Patent Application No. 24575/78 describes a receiver having many features in common with that described herein. WHAT WE CLAIM IS:-

1. A multiband radio receiver having a digitally controlled preset tuning system, in which digital signals for a band and a channel selection are supplied to an up/ down counter having a plurality of stages providing outputs to a digital-to-analog convertor so as to obtain a D.C. voltage signal corresponding to said digital signals,

said D.C. voltage signal being applied to a tuning means of said receiver to select a desired band and to tune to a desired frequency, wherein the impovement is characterized in that said digital-to-analog convertor comprises: a) an oscillator for providing an oscillator signal; b) a pulse synthesizer for receiving said oscillator signal and which provides a serial pulse train by subjecting said oscillator signal to successive frequency divisions, combining the frequency divided signals with respective stages of said counter and synthesizing the combined signals into a rectangular wave synthesizer output; c) A flip-flop circuit one input of which is connected to receive said pulse synthesizer output and another input of which is connected to receive a clock signal; and d) a low pass filter for receiving the output of said flip-íIop circuit, the output of said low pass filter being applied to said tuning means each clock signal occurring before the change of state of said pulse synthesizer to thereby eliminate from the input to said low pass filter any chattering which may occur in the synthesizer output signal.

2. A receiver as defined in Claim 1, wherein said flip-flop is a D-type flip-flop.

3. A receiver as defined in Claim 1, wherein said clock signal is said oscillator signal.

4. A receiver as defined Claim 1, wherein said U/D counter counts pulses from a pulse generator oher than said oscillator.