GB2002967A - Integrated circuit assembly - Google Patents

Integrated circuit assembly

Info

Publication number
GB2002967A
GB2002967A GB7830237A GB7830237A GB2002967A GB 2002967 A GB2002967 A GB 2002967A GB 7830237 A GB7830237 A GB 7830237A GB 7830237 A GB7830237 A GB 7830237A GB 2002967 A GB2002967 A GB 2002967A
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
circuit board
holes
circuit
circuit assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7830237A
Other versions
GB2002967B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Publication of GB2002967A publication Critical patent/GB2002967A/en
Application granted granted Critical
Publication of GB2002967B publication Critical patent/GB2002967B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

An integrated circuit assembly comprises a circuit board one surface of which is provided with a circuit by an etching process. An integrated circuit chip 2 is disposed adjacent to this surface and is mounted between through- holes 1a, 1b in the circuit board 1. Wires 3 are wire bonded to electrodes of the integrated circuit chip 2 and the said circuit to effect electrical connections therebetween. The through-holes 1a, 1b are employed as gates in a transfer moulding process in which there is formed a moulded member 4 between which and the circuit board 1 the integrated circuit chip 2 is encapsulated. Portions of the moulded member 4 extend through the through-holes 1a, 1b and have enlarged parts 4a, 4b which overlie the opposite surface of the circuit board 1 to prevent removal of the moulded members 4 from the circuit board 1. <IMAGE>
GB7830237A 1977-08-19 1978-07-18 Integrated circuit assembly Expired GB2002967B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1977111739U JPS5636140Y2 (en) 1977-08-19 1977-08-19

Publications (2)

Publication Number Publication Date
GB2002967A true GB2002967A (en) 1979-02-28
GB2002967B GB2002967B (en) 1982-01-06

Family

ID=14568949

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7830237A Expired GB2002967B (en) 1977-08-19 1978-07-18 Integrated circuit assembly

Country Status (2)

Country Link
JP (1) JPS5636140Y2 (en)
GB (1) GB2002967B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2204184A (en) * 1987-04-29 1988-11-02 Stanley Bracey Mounting electronic components on substrates

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141338A (en) * 1981-02-26 1982-09-01 Purakoo:Kk Method and apparatus to wind up synthetic resin film
JPH063836B2 (en) * 1982-03-31 1994-01-12 株式会社東芝 Multi-chip module

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5127984B2 (en) * 1973-06-20 1976-08-16

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2204184A (en) * 1987-04-29 1988-11-02 Stanley Bracey Mounting electronic components on substrates

Also Published As

Publication number Publication date
JPS5636140Y2 (en) 1981-08-25
GB2002967B (en) 1982-01-06
JPS5438468U (en) 1979-03-13

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19920718