GB1419906A - Semiconductor devices manufacture - Google Patents
Semiconductor devices manufactureInfo
- Publication number
- GB1419906A GB1419906A GB499574A GB499574A GB1419906A GB 1419906 A GB1419906 A GB 1419906A GB 499574 A GB499574 A GB 499574A GB 499574 A GB499574 A GB 499574A GB 1419906 A GB1419906 A GB 1419906A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- titanium
- insulator
- sputter
- over
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
1419906 Integrated circuit RAYTHEON CO 4 Feb 1974 [12 Feb 1973] 4995/74 Heading H1K In a semiconductor integrated circuit having a first pattern of conductors formed on a first insulator supported on the semiconductor body and contacting active elements through apertures in the insulator, the conductors being formed by depositing conductive material over the first insulator and removing selected regions of this material by sputter etching through a mask which is converted by the sputter etching to a compound which is removed by the sputter etching at a lower rate than the regions of the conductive material, a layer of titanium dioxide is formed over the first conductors by sputter deposition of titanium in an oxidizing atmosphere and a second insulator layer, e.g. of SiO 2 , is formed thereover. The arrangement provides improved bonding between the insulating layers and the conductive pattern and further conductive patterns which are preferably provided over the second insulator. The first conductive pattern comprises a first layer of titanium, a second layer a platinum and a third layer of gold formed by vacuum deposition or sputtering. A layer of titanium or other refractory metal is deposited over the gold and selectively removed by chemical etching through a photoresist mask to form a mask for forming the first conductive pattern. Thus portions of the multilayer conductor are selectively removed by sputter etching in an argon-oxygen atmosphere. The titanium mask and the lower layer of titanium in the multilayer conductor are oxidized in the sputter atmosphere, this titanium dioxide only being slowly removed by the sputter etching which is thus stopped at this stage, the remaining titanium dioxide being removed by chemical etching. A layer of titanium dioxide 100Š thick is then formed over all the exposed surface by sputter deposition of titanium in an oxidizing atmosphere. The second insulator, SiO 2 , is then formed over this TiO 2 layer by chemical vapour or sputter deposition. Subsequent patterns of conductors with interconnections to other patterns may be formed as before over these two insulating layers.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US33151173A | 1973-02-12 | 1973-02-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1419906A true GB1419906A (en) | 1975-12-31 |
Family
ID=23294273
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB499574A Expired GB1419906A (en) | 1973-02-12 | 1974-02-04 | Semiconductor devices manufacture |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS49114381A (en) |
CA (1) | CA1004779A (en) |
DE (1) | DE2406578A1 (en) |
GB (1) | GB1419906A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2137808A (en) * | 1983-04-06 | 1984-10-10 | Plessey Co Plc | Integrated circuit processing method |
-
1974
- 1974-01-29 JP JP1156774A patent/JPS49114381A/ja active Pending
- 1974-02-04 GB GB499574A patent/GB1419906A/en not_active Expired
- 1974-02-07 CA CA192,009A patent/CA1004779A/en not_active Expired
- 1974-02-12 DE DE19742406578 patent/DE2406578A1/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2137808A (en) * | 1983-04-06 | 1984-10-10 | Plessey Co Plc | Integrated circuit processing method |
Also Published As
Publication number | Publication date |
---|---|
CA1004779A (en) | 1977-02-01 |
JPS49114381A (en) | 1974-10-31 |
DE2406578A1 (en) | 1974-08-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |