GB1353366A - Integrated semiconductor read-only storage cell matrices - Google Patents

Integrated semiconductor read-only storage cell matrices

Info

Publication number
GB1353366A
GB1353366A GB4055471A GB4055471A GB1353366A GB 1353366 A GB1353366 A GB 1353366A GB 4055471 A GB4055471 A GB 4055471A GB 4055471 A GB4055471 A GB 4055471A GB 1353366 A GB1353366 A GB 1353366A
Authority
GB
United Kingdom
Prior art keywords
regions
columns
discrete
mask
areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4055471A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1353366A publication Critical patent/GB1353366A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

1353366 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 31 Aug 1971 [2 Sept 1970] 40554/71 Heading H1K Individual storage cells of a semi-conductor read-only memory matrix are in a P-type substrate formed at the intersections of N<SP>+</SP> columns D 1-3 and metallized rows M 1 , M 2 overlying an insulating layer of uniform thickness overlying the entire substrate. The columns D 1 -D 3 provide common drain regions for IGFETs constituting the storage cells of each column of the matrix, source regions being provided by discrete N<SP>+</SP> regions S 11 -S 23 between the columns D 1 -D 3 Discrete metallized areas G 11 -G 23 in lines between the rows M 1 , M 2 form the gates of the IGFETs. Personalization of the memory matrix is effected by design of the contact opening mask, only selected contact areas such as 21-25 being opened. In modifications the same effect is obtained by appropriate design of the gate metallisative mask (certain of the areas G 11 -G 23 being omitted) and/or the source region diffusive mask (selected of the discrete regions S 11 -S 23 being restricted to the area below the corresponding row M 1 , M 2 ).
GB4055471A 1970-09-02 1971-08-31 Integrated semiconductor read-only storage cell matrices Expired GB1353366A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19702043405 DE2043405A1 (en) 1970-09-02 1970-09-02 Semiconductor arrangement with monolithically integrated insulating layer field effect transistors

Publications (1)

Publication Number Publication Date
GB1353366A true GB1353366A (en) 1974-05-15

Family

ID=5781308

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4055471A Expired GB1353366A (en) 1970-09-02 1971-08-31 Integrated semiconductor read-only storage cell matrices

Country Status (8)

Country Link
AU (1) AU3180371A (en)
BE (1) BE770898A (en)
CH (1) CH534431A (en)
DE (1) DE2043405A1 (en)
ES (1) ES394706A1 (en)
FR (1) FR2105176B1 (en)
GB (1) GB1353366A (en)
NL (1) NL7112058A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2572851B1 (en) * 1984-11-08 1987-07-31 Matra Harris Semiconducteurs PREDIFFUSED NETWORK WITH INTERCONNECTABLE BASE CELLS

Also Published As

Publication number Publication date
DE2043405A1 (en) 1972-03-16
FR2105176A1 (en) 1972-04-28
BE770898A (en) 1971-12-16
AU3180371A (en) 1973-02-01
NL7112058A (en) 1972-03-06
ES394706A1 (en) 1975-11-01
FR2105176B1 (en) 1974-10-31
CH534431A (en) 1973-02-28

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee