CH534431A - Semiconductor arrangement with integrated insulated-film field effect transistors - Google Patents

Semiconductor arrangement with integrated insulated-film field effect transistors

Info

Publication number
CH534431A
CH534431A CH1286271A CH1286271A CH534431A CH 534431 A CH534431 A CH 534431A CH 1286271 A CH1286271 A CH 1286271A CH 1286271 A CH1286271 A CH 1286271A CH 534431 A CH534431 A CH 534431A
Authority
CH
Switzerland
Prior art keywords
field effect
effect transistors
semiconductor arrangement
film field
integrated insulated
Prior art date
Application number
CH1286271A
Other languages
German (de)
Inventor
Utz Dr Baitinger
Frantz Hermann
Haug Werner
Rolf Dr Remshardt
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH534431A publication Critical patent/CH534431A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CH1286271A 1970-09-02 1971-09-01 Semiconductor arrangement with integrated insulated-film field effect transistors CH534431A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19702043405 DE2043405A1 (en) 1970-09-02 1970-09-02 Semiconductor arrangement with monolithically integrated insulating layer field effect transistors

Publications (1)

Publication Number Publication Date
CH534431A true CH534431A (en) 1973-02-28

Family

ID=5781308

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1286271A CH534431A (en) 1970-09-02 1971-09-01 Semiconductor arrangement with integrated insulated-film field effect transistors

Country Status (8)

Country Link
AU (1) AU3180371A (en)
BE (1) BE770898A (en)
CH (1) CH534431A (en)
DE (1) DE2043405A1 (en)
ES (1) ES394706A1 (en)
FR (1) FR2105176B1 (en)
GB (1) GB1353366A (en)
NL (1) NL7112058A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2572851B1 (en) * 1984-11-08 1987-07-31 Matra Harris Semiconducteurs PREDIFFUSED NETWORK WITH INTERCONNECTABLE BASE CELLS

Also Published As

Publication number Publication date
FR2105176B1 (en) 1974-10-31
FR2105176A1 (en) 1972-04-28
GB1353366A (en) 1974-05-15
DE2043405A1 (en) 1972-03-16
AU3180371A (en) 1973-02-01
NL7112058A (en) 1972-03-06
BE770898A (en) 1971-12-16
ES394706A1 (en) 1975-11-01

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Legal Events

Date Code Title Description
PL Patent ceased