GB1340653A - Fet read-only storage matrix - Google Patents

Fet read-only storage matrix

Info

Publication number
GB1340653A
GB1340653A GB2434572A GB2434572A GB1340653A GB 1340653 A GB1340653 A GB 1340653A GB 2434572 A GB2434572 A GB 2434572A GB 2434572 A GB2434572 A GB 2434572A GB 1340653 A GB1340653 A GB 1340653A
Authority
GB
United Kingdom
Prior art keywords
type
constituting
substrate
read
strips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2434572A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1340653A publication Critical patent/GB1340653A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

1340653 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 24 May 1972 [5 June 1971] 24345/72 Heading H1K A read-only FET memory matrix includes, in an N (or P) type substrate 1, a plurality of parallel P (N) type bit line strips 2, 3 constituting common source regions for rows of memory cells whose drain regions comprise discrete P (N) type regions 7, 9, and parallel metal word line strips 5 perpendicular to the bit line strips 2, 3 and constituting the gate electrodes of the memory cells. The insulating layer 10 isolating the strips 5 from the substrate 1 and constituting the gate insulation of each wall is thinnest where it overlies the discrete P (N) type drain regions 7, 9 at 12, 14. This allows, for selected cells, a single 'write' process involving the application, between the selected word and bit lines, of a potential sufficient to induce breakdown of the thin portion 12 or 14 of the insulating layer 10, thereby to short the selected drain region 7 or 9 to the metal strip 5 and to charge the memory state of the cell. The channels of the individual cells may be restricted to the areas 16, 18 either by making the insulation 10 relatively thin over these areas, as shown, or by providing heavily-doped N<SP>+</SP> (P<SP>+</SP>) type zones elsewhere in the surface of the substrate 1. The "write" and "read" processes are described in detail, as in the conventional planar process used to manufacture the matrix.
GB2434572A 1971-06-05 1972-05-24 Fet read-only storage matrix Expired GB1340653A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19712128014 DE2128014A1 (en) 1971-06-05 1971-06-05 Solid state memory

Publications (1)

Publication Number Publication Date
GB1340653A true GB1340653A (en) 1973-12-12

Family

ID=5809957

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2434572A Expired GB1340653A (en) 1971-06-05 1972-05-24 Fet read-only storage matrix

Country Status (3)

Country Link
DE (1) DE2128014A1 (en)
FR (1) FR2140542A1 (en)
GB (1) GB1340653A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2270795A (en) * 1992-09-18 1994-03-23 Texas Instruments Ltd Trimming integrated circuits

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1456608A (en) * 1973-08-23 1976-11-24 Ibm Read only memory
US4507757A (en) * 1982-03-23 1985-03-26 Texas Instruments Incorporated Avalanche fuse element in programmable memory
US4507756A (en) * 1982-03-23 1985-03-26 Texas Instruments Incorporated Avalanche fuse element as programmable device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2270795A (en) * 1992-09-18 1994-03-23 Texas Instruments Ltd Trimming integrated circuits
GB2270795B (en) * 1992-09-18 1995-02-15 Texas Instruments Ltd Improvements in or relating to the trimming of integrated circuits

Also Published As

Publication number Publication date
DE2128014B2 (en) 1978-10-05
FR2140542A1 (en) 1973-01-19
DE2128014A1 (en) 1972-12-14
DE2128014C3 (en) 1979-05-31

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees