GB1127101A - Improvements in or relating to synchronising code patten detectors - Google Patents

Abstract

1,127,101. Electric selective signalling. MARCONI CO. Ltd. 20 March, 1967 [16 June, 1966], No. 26832/66. Heading G4H. Also in Division H4] An arrangement for detecting a code pattern of a predetermined sequence of bits, e.g. a synchronizing signal in a p.c.m. system, comprises a shift register having a number of stages which is less then the number of bits in a sequence, means for feeding the sequence to the register, means for shifting the register in steps, in each of which the register registers a different sub-sequence of bits, means for detecting the sub-sequences registered in the successive steps, a counter for counting the steps taken and for providing a pattern recognition signal when a count sufficient to permit registration of the whole pattern has been made, and means for resetting the counter if, at any step in the count, an incorrect sub-sequence combination is registered. As shown in Fig. 1, the synchronizing code, consisting of the sequence 1101010101010101, is fed to a three stage shift register 1 which is shifted step by step by pulses from a unit 2 which are also supplied to an AND gate 3. Three code detectors 5, 6, 7 are connected to the shift register so that they respond to the sub-sequences 110, 101 and 010 respectively. In operation, when the first combination is registered (110) the output of detector 5 switches a bi-stable device 9 which opens AND gate 3. The next pulse from unit 2 steps a 13-step counter via gate 3 and shifts register 1 by one step so that it registers 101. This combination is recognized by detector 6 thus inhibiting gate 8 from providing an output and enabling gate 3 to remain open. Counter 4 is stepped by the next pulse from 2 and the register shifted to register 010, this sequence being recognized by detector 7 so that gate 8 remains inhibited and gate 3 remains open. Detectors 6 and 7 continue to inhibit the gate 8 until the end of the synchronizing signal is reached, a full count is reached at 4 and an output signal is obtained indicating that the correct sync. signal has been received. Should an error occur in the sync. signal, detector 6 or 7 will fail to inhibit the gate 8, bi-stable 9 will be switched over to close gate 3, and the counter 4 will be reset to zero. The detector then awaits the registration of the 110 sequence to restart the count. In a modification, Fig. 2 (not shown), using the same synchronizing code, a two-stage register co-operates with a pair of detectors responding to 11 and 00 respectively. When the initial sequence 11 is detected a bi-stable device is switched to enable an AND gate controlling the counter which continues to count if the correct sync. signal is being received. Should the combination 11 or 00 be detected after the initial sequence a signal is provided via an OR gate to reset the counter.