GB1287330A - Improvements in or relating to digital signal equipment - Google Patents

Abstract

1287330 Digital transmission; synchronizing MARCONI CO Ltd 23 April 1971 [9 July 1970] 33299/70 Heading H4P A digital equipment employing a counter 18 as a source on timing pulses has means independent of the counter for continuously monitoring incoming bit signal streams and responsive to a determined number of identifiable bit signal combinations transmitted at the beginning of a stream for resetting the counter in one step to a predetermined count to achieve correct phasing of the counter with respect to the signals. The determined count may be an "all zeroes" condition. Preferably the identifiable combinations are all similar and correspond to a traffic idle signal having the same number of bits as an intelligence character and the means for resetting the counter may comprise a store register having as many stages as bits in one of combinations. A receiver of known type 1 includes main processor 2 receiving clock signals at bit rate from divider 6 also at character rate through a division counter 8; in the embodiment the division ratio n = 10. To synchronize counter 8, received signals are also fed to n = 10 bit register 13 stepping of which is also controlled by divider 6. On receipt of a predetermined bit combination, e.g. a traffic idle signal, detector 14 changes its output to lead 15D and through normally conductive gate 16 to offset three stage counter 17, assumed initially at 00 which gives an output on lead 20 which closes gate 16. Signals on lead 15D also open gate 21 hence signals from division counter 22 move counter 17 forwards. Counter 22 is fed at bit rate through gate 23 also opened when counter 17 is offset. When detector 14 is not detecting a signal, lead 15F is energized hence opens gate 25 hence admitting reverse count signals from counter 22. At full count a signal on lead 26 resets counter 8 to zero. In operation when the first of a plurality of successive idle characters appear in register 13 a signal on line 15D offsets counter 17 which gives a signal on line 20 closing gate 16 and opening gate 23. The signal on lead 15D also opens gate 21. If the next idle signal is detected by 14 at the correct time, gate 21 will pass one forward count to counter 17. If the next idle signal is not detected gate 25 will be open hence counter 17 will receive a reverse count. When counter 17 is full i.e. when the required number of idle characters had been correctly detected, counter 8 is reset in one step to the "all zeroes" condition by a signal over lead 26.