GB1301206A - A system of time-division multiplex transmission via communications satellites - Google Patents

Abstract

1301206 Satellite communication systems INTERNATIONAL STANDARD ELECTRIC CORP 19 Nov 1970 [22 Nov 1969] 54991/70 Heading H4L In a system of the type disclosed in Specification 1,300,960 in which each signal burst is preceded by a codeword for identifying the start of a burst, and an address code, means are provided at each ground station for detecting the start of the message bursts and the corresponding address signals without knowledge of the order of sequence in a frame or the number of the participating stations. The incoming bit sequence BF is supplied to an address receiver AE which detects the addresses of the originating transmitters under the control of bit clock signal b 1 and from thence to a correlation receiver KE which recognizes the start signal of a message burst. When a start signal is detected, a signal is supplied via output a to a store ZSP comprising a chain of three drift registers controlled by clock t 2 . The bits appearing at the junctions of the shift registers indicate the condition at a predetermined point of each of three successive frames and by a majority decision, i.e. 2 out of 3, the time position at which start signals are to be expected within the current incoming frame is determined at ZME. Since clocks t 1 and t 2 are independent of one another, incoming start signals in successive frames may fall in adjacent time positions and to allow for these slight variations the information is taken off from two adjoining positions of the shift registers at the junctions via OR gates 01, 02, 03. In the case of a positive decision an AND gate U 1 is enabled for a predetermined period via a device ZF and the next start signal from receiver KE transferred via the gate U 1 to the output line BZ and is also fed to the store ZSp. This also enables a gate U 2 and the address signal at detector AE is transferred to an address store ASp divided into three sections which are used cyclically for three consecutive frames, the store ASp being controlled by clock t 3 via a control device St. A device AME makes an address majority decision over three consecutive frames which is then supplied via line A for further processing. In a modification, Fig. 2 (not shown), the stores ZSp and ASp are combined into a single unit.