FR3112894B1 - Procédé de formation d’une tranchée capacitive d’isolation et substrat comprenant une telle tranchée - Google Patents

Procédé de formation d’une tranchée capacitive d’isolation et substrat comprenant une telle tranchée Download PDF

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Publication number
FR3112894B1
FR3112894B1 FR2007905A FR2007905A FR3112894B1 FR 3112894 B1 FR3112894 B1 FR 3112894B1 FR 2007905 A FR2007905 A FR 2007905A FR 2007905 A FR2007905 A FR 2007905A FR 3112894 B1 FR3112894 B1 FR 3112894B1
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France
Prior art keywords
trench
forming
substrate
depositing
cavity
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Active
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FR2007905A
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English (en)
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FR3112894A1 (fr
Inventor
Denis Monnier
Francois Leverd
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STMicroelectronics Crolles 2 SAS
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STMicroelectronics Crolles 2 SAS
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Priority to FR2007905A priority Critical patent/FR3112894B1/fr
Publication of FR3112894A1 publication Critical patent/FR3112894A1/fr
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Publication of FR3112894B1 publication Critical patent/FR3112894B1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Le texte concerne un procédé de formation d’une tranchée d’isolation capacitive dans un substrat semi-conducteur, comprenant les étapes successives suivantes :- le creusement d’une tranchée (10) à partir d’une surface principale du substrat (1), ladite tranchée comprenant une portion supérieure (10a) s’élargissant progressivement à partir d’un col (102) en direction d’une portion inférieure (10b) de la tranchée ;- la formation d’un revêtement en un premier matériau électriquement isolant (14) sur les parois de la tranchée ;- le dépôt d’un premier matériau semi-conducteur (15) sur ledit revêtement, ledit dépôt étant interrompu de sorte à ménager un espace libre entre les parois (100, 101) de la tranchée, ledit espace libre présentant une ouverture (150) au niveau du col (102) ;- le dépôt d’un second matériau électriquement isolant (16) dans la tranchée, ledit dépôt résultant en la formation d’un bouchon (160) obturant ladite ouverture (150) pour former une cavité (17) fermée ;- la gravure du bouchon (16) de sorte à ouvrir la cavité (17) ;- le dépôt d’un second matériau semi-conducteur ou d’un métal de sorte à remplir la cavité (17). Figure pour l’abrégé : Fig 2I
FR2007905A 2020-07-27 2020-07-27 Procédé de formation d’une tranchée capacitive d’isolation et substrat comprenant une telle tranchée Active FR3112894B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR2007905A FR3112894B1 (fr) 2020-07-27 2020-07-27 Procédé de formation d’une tranchée capacitive d’isolation et substrat comprenant une telle tranchée

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2007905A FR3112894B1 (fr) 2020-07-27 2020-07-27 Procédé de formation d’une tranchée capacitive d’isolation et substrat comprenant une telle tranchée
FR2007905 2020-07-27

Publications (2)

Publication Number Publication Date
FR3112894A1 FR3112894A1 (fr) 2022-01-28
FR3112894B1 true FR3112894B1 (fr) 2023-04-21

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FR2007905A Active FR3112894B1 (fr) 2020-07-27 2020-07-27 Procédé de formation d’une tranchée capacitive d’isolation et substrat comprenant une telle tranchée

Country Status (1)

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FR (1) FR3112894B1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2826179A1 (fr) * 2001-06-14 2002-12-20 St Microelectronics Sa Tranchee d'isolement profonde et procede de realisation
KR102209097B1 (ko) * 2014-02-27 2021-01-28 삼성전자주식회사 이미지 센서 및 이의 제조 방법
KR102318197B1 (ko) * 2014-09-22 2021-10-26 삼성전자주식회사 씨모스 이미지 센서의 픽셀 및 이를 포함하는 이미지 센서
FR3026891A1 (fr) * 2014-10-06 2016-04-08 St Microelectronics Crolles 2 Sas Dispositif d'imagerie integre a illumination face arriere avec routage d'interconnexion simplifie
US11302734B2 (en) * 2018-06-29 2022-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Deep trench isolation structures resistant to cracking

Also Published As

Publication number Publication date
FR3112894A1 (fr) 2022-01-28

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