FR3104811B1 - Procédé de fabrication d’un substrat RF-SOI à couche de piégeage issue d’une transformation cristalline d’une couche enterrée - Google Patents

Procédé de fabrication d’un substrat RF-SOI à couche de piégeage issue d’une transformation cristalline d’une couche enterrée Download PDF

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Publication number
FR3104811B1
FR3104811B1 FR1914563A FR1914563A FR3104811B1 FR 3104811 B1 FR3104811 B1 FR 3104811B1 FR 1914563 A FR1914563 A FR 1914563A FR 1914563 A FR1914563 A FR 1914563A FR 3104811 B1 FR3104811 B1 FR 3104811B1
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France
Prior art keywords
manufacturing
soi substrate
crystalline transformation
substrate
support substrate
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FR1914563A
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English (en)
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FR3104811A1 (fr
Inventor
Shay Reboh
Alba Pablo Acosta
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Priority to FR1914563A priority Critical patent/FR3104811B1/fr
Priority to US17/124,184 priority patent/US11469137B2/en
Priority to EP20214522.3A priority patent/EP3840033A1/fr
Publication of FR3104811A1 publication Critical patent/FR3104811A1/fr
Application granted granted Critical
Publication of FR3104811B1 publication Critical patent/FR3104811B1/fr
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)

Abstract

L’invention porte sur un procédé de fabrication d’un substrat de type semi-conducteur sur isolant pour applications radiofréquences, comprenant les étapes de collage direct d’un substrat support (1) comportant une région de piégeage de charges électriques (4) et d’un substrat donneur (5) comportant une couche mince (7) d’un matériau semi-conducteur, une ou plusieurs couches de matériau diélectrique (2) étant à l’interface ; et de report de ladite couche mince (7) sur le substrat support. La région de piégeage de charges électriques est formée par transformation cristalline d’une zone enterrée du substrat support. Figure pour l’abrégé : figure 2
FR1914563A 2019-12-17 2019-12-17 Procédé de fabrication d’un substrat RF-SOI à couche de piégeage issue d’une transformation cristalline d’une couche enterrée Active FR3104811B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1914563A FR3104811B1 (fr) 2019-12-17 2019-12-17 Procédé de fabrication d’un substrat RF-SOI à couche de piégeage issue d’une transformation cristalline d’une couche enterrée
US17/124,184 US11469137B2 (en) 2019-12-17 2020-12-16 Manufacturing process of an RF-SOI trapping layer substrate resulting from a crystalline transformation of a buried layer
EP20214522.3A EP3840033A1 (fr) 2019-12-17 2020-12-16 Procédé de fabrication d'un substrat rf-soi à couche de piégeage issue d'une transformation cristalline d'une couche enterrée

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1914563A FR3104811B1 (fr) 2019-12-17 2019-12-17 Procédé de fabrication d’un substrat RF-SOI à couche de piégeage issue d’une transformation cristalline d’une couche enterrée
FR1914563 2019-12-17

Publications (2)

Publication Number Publication Date
FR3104811A1 FR3104811A1 (fr) 2021-06-18
FR3104811B1 true FR3104811B1 (fr) 2023-04-28

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FR1914563A Active FR3104811B1 (fr) 2019-12-17 2019-12-17 Procédé de fabrication d’un substrat RF-SOI à couche de piégeage issue d’une transformation cristalline d’une couche enterrée

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FR (1) FR3104811B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3108787B1 (fr) * 2020-03-31 2022-04-01 Commissariat Energie Atomique Procédé basse température de transfert et de guérison d’une couche semi-conductrice
FR3116151A1 (fr) * 2020-11-10 2022-05-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de formation d’une structure de piegeage d’un substrat utile

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060118437A (ko) 2003-09-26 2006-11-23 위니베르시트카솔리끄드루뱅 저항손을 감소시키는 다층 반도체 구조의 제조 방법
US8377804B2 (en) * 2008-10-02 2013-02-19 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor substrate and semiconductor device
WO2016081313A1 (fr) * 2014-11-18 2016-05-26 Sunedison Semiconductor Limited Procédé de fabrication de plaquettes de semi-conducteur sur isolant à haute résistivité comprenant couches de piégeage de charges
JP6344271B2 (ja) * 2015-03-06 2018-06-20 信越半導体株式会社 貼り合わせ半導体ウェーハ及び貼り合わせ半導体ウェーハの製造方法
FR3067517B1 (fr) * 2017-06-13 2019-07-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives Substrat soi compatible avec les technologies rfsoi et fdsoi

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Publication number Publication date
FR3104811A1 (fr) 2021-06-18

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