FR3012665A1 - - Google Patents

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Publication number
FR3012665A1
FR3012665A1 FR1360673A FR1360673A FR3012665A1 FR 3012665 A1 FR3012665 A1 FR 3012665A1 FR 1360673 A FR1360673 A FR 1360673A FR 1360673 A FR1360673 A FR 1360673A FR 3012665 A1 FR3012665 A1 FR 3012665A1
Authority
FR
France
Prior art keywords
trenches
semiconductor layer
layer
semiconductor
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR1360673A
Other languages
English (en)
French (fr)
Inventor
Olivier Nier
Denis Rideau
Pierre Morin
Emmanuel Josse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
STMicroelectronics Crolles 2 SAS
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics SA
STMicroelectronics Crolles 2 SAS
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA, STMicroelectronics Crolles 2 SAS, STMicroelectronics lnc USA filed Critical STMicroelectronics SA
Priority to FR1360673A priority Critical patent/FR3012665A1/fr
Priority to US14/526,053 priority patent/US9318372B2/en
Publication of FR3012665A1 publication Critical patent/FR3012665A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/795—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in lateral device isolation regions, e.g. STI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/796—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/011—Manufacture or treatment comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6544—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
FR1360673A 2013-10-31 2013-10-31 Withdrawn FR3012665A1 (enExample)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1360673A FR3012665A1 (enExample) 2013-10-31 2013-10-31
US14/526,053 US9318372B2 (en) 2013-10-31 2014-10-28 Method of stressing a semiconductor layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1360673A FR3012665A1 (enExample) 2013-10-31 2013-10-31

Publications (1)

Publication Number Publication Date
FR3012665A1 true FR3012665A1 (enExample) 2015-05-01

Family

ID=50069108

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1360673A Withdrawn FR3012665A1 (enExample) 2013-10-31 2013-10-31

Country Status (2)

Country Link
US (1) US9318372B2 (enExample)
FR (1) FR3012665A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3012667A1 (enExample) * 2013-10-31 2015-05-01 St Microelectronics Crolles 2
US9607901B2 (en) * 2015-05-06 2017-03-28 Stmicroelectronics, Inc. Integrated tensile strained silicon NFET and compressive strained silicon-germanium PFET implemented in FINFET technology
US10192985B2 (en) * 2015-07-21 2019-01-29 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET with doped isolation insulating layer
TWI582955B (zh) * 2015-09-04 2017-05-11 旺宏電子股份有限公司 隔離結構及其製造方法
CN106531680A (zh) * 2015-09-09 2017-03-22 旺宏电子股份有限公司 隔离结构及其制造方法
FR3046291B1 (fr) * 2015-12-24 2018-02-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Circuit electronique comprenant des tranchees d'isolation electrique
FR3046292B1 (fr) 2015-12-24 2018-02-16 Aledia Circuit electronique comprenant des tranchees d'isolation electrique
CN108780813B (zh) * 2016-04-01 2022-10-11 英特尔公司 具有热性能提升的晶体管
FR3059464B1 (fr) * 2016-11-29 2019-03-15 Commissariat A L'energie Atomique Et Aux Energies Alternatives Circuit electronique comprenant des tranchees d'isolation electrique
US10770571B2 (en) * 2018-09-19 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET with dummy fins and methods of making the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050133864A1 (en) * 2003-12-19 2005-06-23 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US20090057775A1 (en) * 2007-09-04 2009-03-05 Eun Jong Shin Semiconductor Device and Method for Manufacturing Semiconductor Device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0152345B1 (ko) * 1995-06-14 1998-10-01 김광호 혼성 쇼트키 주입 전계 효과 트랜지스터
US5902128A (en) 1996-10-17 1999-05-11 Micron Technology, Inc. Process to improve the flow of oxide during field oxidation by fluorine doping
US7727856B2 (en) 2006-12-24 2010-06-01 Chartered Semiconductor Manufacturing, Ltd. Selective STI stress relaxation through ion implantation
US7700416B1 (en) 2008-04-25 2010-04-20 Acorn Technologies, Inc. Tensile strained semiconductor on insulator using elastic edge relaxation and a sacrificial stressor layer
US8395213B2 (en) 2010-08-27 2013-03-12 Acorn Technologies, Inc. Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
CN102456577B (zh) 2010-10-29 2014-10-01 中国科学院微电子研究所 应力隔离沟槽半导体器件的形成方法
CN102412184B (zh) 2011-05-23 2014-03-12 上海华力微电子有限公司 离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050133864A1 (en) * 2003-12-19 2005-06-23 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US20090057775A1 (en) * 2007-09-04 2009-03-05 Eun Jong Shin Semiconductor Device and Method for Manufacturing Semiconductor Device

Also Published As

Publication number Publication date
US9318372B2 (en) 2016-04-19
US20150118823A1 (en) 2015-04-30

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Effective date: 20150630