FR3012667A1 - - Google Patents
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- Publication number
- FR3012667A1 FR3012667A1 FR1360676A FR1360676A FR3012667A1 FR 3012667 A1 FR3012667 A1 FR 3012667A1 FR 1360676 A FR1360676 A FR 1360676A FR 1360676 A FR1360676 A FR 1360676A FR 3012667 A1 FR3012667 A1 FR 3012667A1
- Authority
- FR
- France
- Prior art keywords
- trenches
- semiconductor layer
- transistor
- layer
- isolation trenches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/795—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in lateral device isolation regions, e.g. STI
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/796—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0151—Manufacturing their isolation regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/011—Manufacture or treatment comprising FinFETs
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- H10P14/3411—
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- H10P14/6544—
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- H10P30/20—
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- H10P30/40—
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- H10P50/692—
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- H10P95/00—
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- H10W10/014—
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- H10W10/0148—
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- H10W10/17—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
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- H10P30/204—
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- H10P30/208—
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- H10P95/90—
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Element Separation (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1360676A FR3012667A1 (enExample) | 2013-10-31 | 2013-10-31 | |
| US14/526,081 US9543214B2 (en) | 2013-10-31 | 2014-10-28 | Method of forming stressed semiconductor layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1360676A FR3012667A1 (enExample) | 2013-10-31 | 2013-10-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR3012667A1 true FR3012667A1 (enExample) | 2015-05-01 |
Family
ID=50069110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR1360676A Withdrawn FR3012667A1 (enExample) | 2013-10-31 | 2013-10-31 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9543214B2 (enExample) |
| FR (1) | FR3012667A1 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9324618B1 (en) * | 2015-06-01 | 2016-04-26 | Globalfoundries Inc. | Methods of forming replacement fins for a FinFET device |
| US9536990B2 (en) | 2015-06-01 | 2017-01-03 | Globalfoundries Inc. | Methods of forming replacement fins for a FinFET device using a targeted thickness for the patterned fin etch mask |
| FR3098645A1 (fr) * | 2019-07-11 | 2021-01-15 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procédé de formation de tranchées |
| US12424482B2 (en) * | 2022-12-12 | 2025-09-23 | Applied Materials, Inc. | Selective implantation into STI of ETSOI device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080150037A1 (en) * | 2006-12-24 | 2008-06-26 | Chartered Semiconductor Manufacturing, Ltd | Selective STI Stress Relaxation Through Ion Implantation |
| US20120108032A1 (en) * | 2010-10-29 | 2012-05-03 | Institute of Microelectronics, Chinese Academy of Sciences | Method for forming a semiconductor device with stressed trench isolation |
| US20120302038A1 (en) * | 2011-05-23 | 2012-11-29 | Shanghai Huali Microelectronics Corporation | Method for preparing a shallow trench isolation structure with the stress of its isolation oxide being tuned by ion implantation |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0152345B1 (ko) | 1995-06-14 | 1998-10-01 | 김광호 | 혼성 쇼트키 주입 전계 효과 트랜지스터 |
| US5902128A (en) | 1996-10-17 | 1999-05-11 | Micron Technology, Inc. | Process to improve the flow of oxide during field oxidation by fluorine doping |
| JP2005183686A (ja) | 2003-12-19 | 2005-07-07 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| US7704818B2 (en) | 2007-09-04 | 2010-04-27 | Dongbu Hitek Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| US7700416B1 (en) | 2008-04-25 | 2010-04-20 | Acorn Technologies, Inc. | Tensile strained semiconductor on insulator using elastic edge relaxation and a sacrificial stressor layer |
| US8395213B2 (en) | 2010-08-27 | 2013-03-12 | Acorn Technologies, Inc. | Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer |
| FR3009647A1 (enExample) * | 2013-08-06 | 2015-02-13 | St Microelectronics Sa | |
| FR3009646A1 (enExample) * | 2013-08-06 | 2015-02-13 | St Microelectronics Sa | |
| FR3012665A1 (enExample) * | 2013-10-31 | 2015-05-01 | St Microelectronics Crolles 2 | |
| FR3012666A1 (enExample) * | 2013-10-31 | 2015-05-01 | St Microelectronics Crolles 2 |
-
2013
- 2013-10-31 FR FR1360676A patent/FR3012667A1/fr not_active Withdrawn
-
2014
- 2014-10-28 US US14/526,081 patent/US9543214B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080150037A1 (en) * | 2006-12-24 | 2008-06-26 | Chartered Semiconductor Manufacturing, Ltd | Selective STI Stress Relaxation Through Ion Implantation |
| US20120108032A1 (en) * | 2010-10-29 | 2012-05-03 | Institute of Microelectronics, Chinese Academy of Sciences | Method for forming a semiconductor device with stressed trench isolation |
| US20120302038A1 (en) * | 2011-05-23 | 2012-11-29 | Shanghai Huali Microelectronics Corporation | Method for preparing a shallow trench isolation structure with the stress of its isolation oxide being tuned by ion implantation |
Also Published As
| Publication number | Publication date |
|---|---|
| US9543214B2 (en) | 2017-01-10 |
| US20150118805A1 (en) | 2015-04-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |
Effective date: 20150630 |