FR2921201B1 - Procede de collage de puces sur un substrat de contrainte et procede de mise sous contrainte d'un circuit de lecture semi-conducteur - Google Patents

Procede de collage de puces sur un substrat de contrainte et procede de mise sous contrainte d'un circuit de lecture semi-conducteur

Info

Publication number
FR2921201B1
FR2921201B1 FR0757676A FR0757676A FR2921201B1 FR 2921201 B1 FR2921201 B1 FR 2921201B1 FR 0757676 A FR0757676 A FR 0757676A FR 0757676 A FR0757676 A FR 0757676A FR 2921201 B1 FR2921201 B1 FR 2921201B1
Authority
FR
France
Prior art keywords
reading circuit
substrate
stucking
adhesive
bonding chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0757676A
Other languages
English (en)
French (fr)
Other versions
FR2921201A1 (fr
Inventor
Manuel Fendler
Mani Abdenacer Ait
Alain Gueugnot
Francois Marion
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR0757676A priority Critical patent/FR2921201B1/fr
Priority to EP08164325.6A priority patent/EP2040291B1/fr
Priority to US12/212,302 priority patent/US7645686B2/en
Priority to JP2008241065A priority patent/JP5557436B2/ja
Publication of FR2921201A1 publication Critical patent/FR2921201A1/fr
Application granted granted Critical
Publication of FR2921201B1 publication Critical patent/FR2921201B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/018—Manufacture or treatment of image sensors covered by group H10F39/12 of hybrid image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7428—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7438—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors

Landscapes

  • Wire Bonding (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Micromachines (AREA)
FR0757676A 2007-09-19 2007-09-19 Procede de collage de puces sur un substrat de contrainte et procede de mise sous contrainte d'un circuit de lecture semi-conducteur Expired - Fee Related FR2921201B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR0757676A FR2921201B1 (fr) 2007-09-19 2007-09-19 Procede de collage de puces sur un substrat de contrainte et procede de mise sous contrainte d'un circuit de lecture semi-conducteur
EP08164325.6A EP2040291B1 (fr) 2007-09-19 2008-09-15 Procédé de collage de puces sur un substrat de contrainte et procédé de mise sous contrainte d'un circuit de lecture semi-conducteur
US12/212,302 US7645686B2 (en) 2007-09-19 2008-09-17 Method of bonding chips on a strained substrate and method of placing under strain a semiconductor reading circuit
JP2008241065A JP5557436B2 (ja) 2007-09-19 2008-09-19 チップ形成方法、及び、チップを基板にボンディングする方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0757676A FR2921201B1 (fr) 2007-09-19 2007-09-19 Procede de collage de puces sur un substrat de contrainte et procede de mise sous contrainte d'un circuit de lecture semi-conducteur

Publications (2)

Publication Number Publication Date
FR2921201A1 FR2921201A1 (fr) 2009-03-20
FR2921201B1 true FR2921201B1 (fr) 2009-12-18

Family

ID=39271531

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0757676A Expired - Fee Related FR2921201B1 (fr) 2007-09-19 2007-09-19 Procede de collage de puces sur un substrat de contrainte et procede de mise sous contrainte d'un circuit de lecture semi-conducteur

Country Status (4)

Country Link
US (1) US7645686B2 (https=)
EP (1) EP2040291B1 (https=)
JP (1) JP5557436B2 (https=)
FR (1) FR2921201B1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2961519B1 (fr) 2010-06-18 2012-07-06 Commissariat Energie Atomique Procede de collage calibre en epaisseur entre au moins deux substrats
US10374000B2 (en) 2013-09-23 2019-08-06 Teledyne Scientific & Imaging, Llc Thermal-contraction matched hybrid device package

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365088A (en) 1988-08-02 1994-11-15 Santa Barbara Research Center Thermal/mechanical buffer for HgCdTe/Si direct hybridization
JPH02271558A (ja) * 1989-04-12 1990-11-06 Mitsubishi Electric Corp 半導体装置及びその製造方法
US4943491A (en) * 1989-11-20 1990-07-24 Honeywell Inc. Structure for improving interconnect reliability of focal plane arrays
JP2564694B2 (ja) * 1990-09-10 1996-12-18 ローム株式会社 半導体素子の製造方法
EP0829907A1 (en) 1996-09-16 1998-03-18 Rockwell International Corporation Hybrid focal plane array comprising stabilizing structure
JP3410371B2 (ja) * 1998-08-18 2003-05-26 リンテック株式会社 ウエハ裏面研削時の表面保護シートおよびその利用方法
US6255140B1 (en) * 1998-10-19 2001-07-03 Industrial Technology Research Institute Flip chip chip-scale package
FR2810454B1 (fr) * 2000-06-15 2003-07-18 Sofradir Detecteur de rayonnements electromagnetiques, et notamment de rayonnements infrarouges, et procede pour la realisation d'un tel detecteur
US6407381B1 (en) * 2000-07-05 2002-06-18 Amkor Technology, Inc. Wafer scale image sensor package
JP3719921B2 (ja) * 2000-09-29 2005-11-24 株式会社東芝 半導体装置及びその製造方法
TW522531B (en) * 2000-10-20 2003-03-01 Matsushita Electric Industrial Co Ltd Semiconductor device, method of manufacturing the device and mehtod of mounting the device
JP5022552B2 (ja) * 2002-09-26 2012-09-12 セイコーエプソン株式会社 電気光学装置の製造方法及び電気光学装置
FR2857508B1 (fr) * 2003-07-09 2005-09-09 Fr De Detecteurs Infrarouges S Procede pour la realisation d'un detecteur de rayonnements electromagnetiques, et notamment de rayonnements infrarouges, et detecteur ontenu au moyen de ce procede
JP4396472B2 (ja) * 2004-10-06 2010-01-13 パナソニック株式会社 薄膜状素子の転写方法
JP4745073B2 (ja) * 2006-02-03 2011-08-10 シチズン電子株式会社 表面実装型発光素子の製造方法
TWI463580B (zh) * 2007-06-19 2014-12-01 瑞薩科技股份有限公司 Manufacturing method of semiconductor integrated circuit device

Also Published As

Publication number Publication date
US7645686B2 (en) 2010-01-12
EP2040291A1 (fr) 2009-03-25
FR2921201A1 (fr) 2009-03-20
EP2040291B1 (fr) 2018-03-14
US20090075423A1 (en) 2009-03-19
JP2009076915A (ja) 2009-04-09
JP5557436B2 (ja) 2014-07-23

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Legal Events

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Year of fee payment: 10

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Effective date: 20200914