JP5557436B2 - チップ形成方法、及び、チップを基板にボンディングする方法 - Google Patents

チップ形成方法、及び、チップを基板にボンディングする方法 Download PDF

Info

Publication number
JP5557436B2
JP5557436B2 JP2008241065A JP2008241065A JP5557436B2 JP 5557436 B2 JP5557436 B2 JP 5557436B2 JP 2008241065 A JP2008241065 A JP 2008241065A JP 2008241065 A JP2008241065 A JP 2008241065A JP 5557436 B2 JP5557436 B2 JP 5557436B2
Authority
JP
Japan
Prior art keywords
substrate
chip
adhesive
bonding
space
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008241065A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009076915A5 (https=
JP2009076915A (ja
Inventor
マニュエル フェンドラー
アブドナセール エ−マニ
アラン ググノー
フランソワ マリオン
Original Assignee
コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ filed Critical コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ
Publication of JP2009076915A publication Critical patent/JP2009076915A/ja
Publication of JP2009076915A5 publication Critical patent/JP2009076915A5/ja
Application granted granted Critical
Publication of JP5557436B2 publication Critical patent/JP5557436B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/018—Manufacture or treatment of image sensors covered by group H10F39/12 of hybrid image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7428—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7438—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors

Landscapes

  • Wire Bonding (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Micromachines (AREA)
JP2008241065A 2007-09-19 2008-09-19 チップ形成方法、及び、チップを基板にボンディングする方法 Active JP5557436B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0757676 2007-09-19
FR0757676A FR2921201B1 (fr) 2007-09-19 2007-09-19 Procede de collage de puces sur un substrat de contrainte et procede de mise sous contrainte d'un circuit de lecture semi-conducteur

Publications (3)

Publication Number Publication Date
JP2009076915A JP2009076915A (ja) 2009-04-09
JP2009076915A5 JP2009076915A5 (https=) 2011-11-04
JP5557436B2 true JP5557436B2 (ja) 2014-07-23

Family

ID=39271531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008241065A Active JP5557436B2 (ja) 2007-09-19 2008-09-19 チップ形成方法、及び、チップを基板にボンディングする方法

Country Status (4)

Country Link
US (1) US7645686B2 (https=)
EP (1) EP2040291B1 (https=)
JP (1) JP5557436B2 (https=)
FR (1) FR2921201B1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2961519B1 (fr) 2010-06-18 2012-07-06 Commissariat Energie Atomique Procede de collage calibre en epaisseur entre au moins deux substrats
US10374000B2 (en) 2013-09-23 2019-08-06 Teledyne Scientific & Imaging, Llc Thermal-contraction matched hybrid device package

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365088A (en) 1988-08-02 1994-11-15 Santa Barbara Research Center Thermal/mechanical buffer for HgCdTe/Si direct hybridization
JPH02271558A (ja) * 1989-04-12 1990-11-06 Mitsubishi Electric Corp 半導体装置及びその製造方法
US4943491A (en) * 1989-11-20 1990-07-24 Honeywell Inc. Structure for improving interconnect reliability of focal plane arrays
JP2564694B2 (ja) * 1990-09-10 1996-12-18 ローム株式会社 半導体素子の製造方法
EP0829907A1 (en) 1996-09-16 1998-03-18 Rockwell International Corporation Hybrid focal plane array comprising stabilizing structure
JP3410371B2 (ja) * 1998-08-18 2003-05-26 リンテック株式会社 ウエハ裏面研削時の表面保護シートおよびその利用方法
US6255140B1 (en) * 1998-10-19 2001-07-03 Industrial Technology Research Institute Flip chip chip-scale package
FR2810454B1 (fr) * 2000-06-15 2003-07-18 Sofradir Detecteur de rayonnements electromagnetiques, et notamment de rayonnements infrarouges, et procede pour la realisation d'un tel detecteur
US6407381B1 (en) * 2000-07-05 2002-06-18 Amkor Technology, Inc. Wafer scale image sensor package
JP3719921B2 (ja) * 2000-09-29 2005-11-24 株式会社東芝 半導体装置及びその製造方法
TW522531B (en) * 2000-10-20 2003-03-01 Matsushita Electric Industrial Co Ltd Semiconductor device, method of manufacturing the device and mehtod of mounting the device
JP5022552B2 (ja) * 2002-09-26 2012-09-12 セイコーエプソン株式会社 電気光学装置の製造方法及び電気光学装置
FR2857508B1 (fr) * 2003-07-09 2005-09-09 Fr De Detecteurs Infrarouges S Procede pour la realisation d'un detecteur de rayonnements electromagnetiques, et notamment de rayonnements infrarouges, et detecteur ontenu au moyen de ce procede
JP4396472B2 (ja) * 2004-10-06 2010-01-13 パナソニック株式会社 薄膜状素子の転写方法
JP4745073B2 (ja) * 2006-02-03 2011-08-10 シチズン電子株式会社 表面実装型発光素子の製造方法
TWI463580B (zh) * 2007-06-19 2014-12-01 瑞薩科技股份有限公司 Manufacturing method of semiconductor integrated circuit device

Also Published As

Publication number Publication date
FR2921201B1 (fr) 2009-12-18
US7645686B2 (en) 2010-01-12
EP2040291A1 (fr) 2009-03-25
FR2921201A1 (fr) 2009-03-20
EP2040291B1 (fr) 2018-03-14
US20090075423A1 (en) 2009-03-19
JP2009076915A (ja) 2009-04-09

Similar Documents

Publication Publication Date Title
US10763185B2 (en) Packaged semiconductor components having substantially rigid support members
Lau Evolution, challenge, and outlook of TSV, 3D IC integration and 3D silicon integration
US9196594B2 (en) Chip package and method for forming the same
US7875481B2 (en) Semiconductor apparatus and method for manufacturing the same
US7619315B2 (en) Stack type semiconductor chip package having different type of chips and fabrication method thereof
US20090039527A1 (en) Sensor-type package and method for fabricating the same
WO2017177631A1 (zh) 影像传感芯片的封装结构及其制作方法
US8178391B2 (en) Method for packaging semiconductors at wafer level
US9799588B2 (en) Chip package and manufacturing method thereof
TW201227937A (en) Image sensor chip package and method for forming the same
CN110015634B (zh) 在前端中在晶片级沉积保护材料以进行早期颗粒和水分保护
US20090321867A1 (en) Method for production of packaged electronic components, and a packaged electronic component
JP5557436B2 (ja) チップ形成方法、及び、チップを基板にボンディングする方法
US20080079125A1 (en) Microelectronic die assembly having thermally conductive element at a backside thereof and method of making same
KR100666919B1 (ko) 반도체 패키지용 접착 시트, 이를 포함하는 반도체 소자,이를 포함하는 멀티 스택 패키지, 반도체 소자의 제조 방법및 멀티 스택 패키지의 제조 방법
US7998834B2 (en) Substrate level bonding method and substrate level package
US7696008B2 (en) Wafer-level chip packaging process and chip package structure
US20130062720A1 (en) Extended area cover plate for integrated infrared sensor
KR20060085848A (ko) 뒷면 연마 후 범프 형성 공정을 포함하는 반도체 웨이퍼제조 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110915

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110915

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130129

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130205

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20130501

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20130508

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20130605

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20130610

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130704

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140121

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140417

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140513

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140603

R150 Certificate of patent or registration of utility model

Ref document number: 5557436

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250