FR2755297B1 - Procede de formation d'un cablage multicouche dans un composant a semiconducteur - Google Patents

Procede de formation d'un cablage multicouche dans un composant a semiconducteur

Info

Publication number
FR2755297B1
FR2755297B1 FR9706985A FR9706985A FR2755297B1 FR 2755297 B1 FR2755297 B1 FR 2755297B1 FR 9706985 A FR9706985 A FR 9706985A FR 9706985 A FR9706985 A FR 9706985A FR 2755297 B1 FR2755297 B1 FR 2755297B1
Authority
FR
France
Prior art keywords
forming
semiconductor component
multilayer wiring
multilayer
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9706985A
Other languages
English (en)
Other versions
FR2755297A1 (fr
Inventor
Young Hun Park
Sung Hoon Ko
Jong Seob Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2755297A1 publication Critical patent/FR2755297A1/fr
Application granted granted Critical
Publication of FR2755297B1 publication Critical patent/FR2755297B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/94—Laser ablative material removal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/963—Removing process residues from vertical substrate surfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR9706985A 1996-10-28 1997-06-05 Procede de formation d'un cablage multicouche dans un composant a semiconducteur Expired - Fee Related FR2755297B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960049351A KR100219562B1 (ko) 1996-10-28 1996-10-28 반도체장치의 다층 배선 형성방법

Publications (2)

Publication Number Publication Date
FR2755297A1 FR2755297A1 (fr) 1998-04-30
FR2755297B1 true FR2755297B1 (fr) 1999-09-24

Family

ID=19479387

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9706985A Expired - Fee Related FR2755297B1 (fr) 1996-10-28 1997-06-05 Procede de formation d'un cablage multicouche dans un composant a semiconducteur

Country Status (7)

Country Link
US (1) US6043165A (fr)
JP (1) JPH10135210A (fr)
KR (1) KR100219562B1 (fr)
DE (1) DE19723708A1 (fr)
FR (1) FR2755297B1 (fr)
GB (1) GB2318908B (fr)
TW (1) TW373314B (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734120B1 (en) * 1999-02-19 2004-05-11 Axcelis Technologies, Inc. Method of photoresist ash residue removal
US6355576B1 (en) * 1999-04-26 2002-03-12 Vlsi Technology Inc. Method for cleaning integrated circuit bonding pads
US6512198B2 (en) 2001-05-15 2003-01-28 Lexmark International, Inc Removal of debris from laser ablated nozzle plates
US20040099283A1 (en) * 2002-11-26 2004-05-27 Axcelis Technologies, Inc. Drying process for low-k dielectric films
DE10310716B4 (de) * 2002-12-23 2005-07-28 Infineon Technologies Ag Verfahren zur Herstellung von Justiermarken auf Halbleiterscheiben
JP2005159294A (ja) * 2003-09-18 2005-06-16 Nec Kagoshima Ltd 基板処理方法及びそれに用いる薬液
US7875602B2 (en) * 2005-10-21 2011-01-25 Sutter West Bay Hospitals Camptothecin derivatives as chemoradiosensitizing agents
CN104078415A (zh) * 2013-03-28 2014-10-01 中芯国际集成电路制造(上海)有限公司 互连结构的制造方法
US10867843B2 (en) * 2016-12-05 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system for fabrication semiconductor device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6331137A (ja) * 1986-07-25 1988-02-09 Hitachi Ltd 多層配線用層間絶縁膜の形成方法
JPH02100342A (ja) * 1988-10-06 1990-04-12 Fuji Xerox Co Ltd 半導体装置の製造方法
CA2009518C (fr) * 1990-02-07 2000-10-17 Luc Ouellet Methode de fabrication de dispositifs a semiconducteur par depot d'une couche de spin sur verre
JPH0464234A (ja) * 1990-07-04 1992-02-28 Mitsubishi Electric Corp 配線パターンの形成方法
JPH05243402A (ja) * 1992-03-03 1993-09-21 Nec Corp 半導体装置の製造方法
EP0564136B1 (fr) * 1992-03-31 1998-06-03 STMicroelectronics, Inc. Méthode de planarisation d'un circuit intégré
EP0608628A3 (fr) * 1992-12-25 1995-01-18 Kawasaki Steel Co Procédé pour fabriquer un dispositif semi-conducteur ayant une structure d'interconnexion multi-couches.
JPH06216264A (ja) * 1993-01-18 1994-08-05 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH08153707A (ja) * 1994-11-29 1996-06-11 Nec Corp 半導体装置の製造方法
JP2727984B2 (ja) * 1994-11-29 1998-03-18 日本電気株式会社 半導体装置の製造方法
US5679211A (en) * 1995-09-18 1997-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Spin-on-glass etchback planarization process using an oxygen plasma to remove an etchback polymer residue

Also Published As

Publication number Publication date
JPH10135210A (ja) 1998-05-22
TW373314B (en) 1999-11-01
FR2755297A1 (fr) 1998-04-30
GB9711078D0 (en) 1997-07-23
KR100219562B1 (ko) 1999-09-01
GB2318908B (en) 2002-01-02
GB2318908A (en) 1998-05-06
US6043165A (en) 2000-03-28
KR19980030015A (ko) 1998-07-25
DE19723708A1 (de) 1998-04-30

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Legal Events

Date Code Title Description
TP Transmission of property

Owner name: MOSAID TECHNOLOGIES INCORPORATED, CA

Effective date: 20111110

CA Change of address

Effective date: 20141021

CD Change of name or company name

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT IN, CA

Effective date: 20141021

ST Notification of lapse

Effective date: 20160229