FR2616965A1 - Interconnexion par montage en pont exterieur sur un substrat semi-conducteur - Google Patents

Interconnexion par montage en pont exterieur sur un substrat semi-conducteur Download PDF

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Publication number
FR2616965A1
FR2616965A1 FR8808159A FR8808159A FR2616965A1 FR 2616965 A1 FR2616965 A1 FR 2616965A1 FR 8808159 A FR8808159 A FR 8808159A FR 8808159 A FR8808159 A FR 8808159A FR 2616965 A1 FR2616965 A1 FR 2616965A1
Authority
FR
France
Prior art keywords
elements
bridge
layer
bridge support
support elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8808159A
Other languages
English (en)
French (fr)
Other versions
FR2616965B1 (https=
Inventor
Hiroshi Matsuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of FR2616965A1 publication Critical patent/FR2616965A1/fr
Application granted granted Critical
Publication of FR2616965B1 publication Critical patent/FR2616965B1/fr
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H10W20/432—Layouts of interconnections comprising crossing interconnections

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR8808159A 1987-06-19 1988-06-17 Interconnexion par montage en pont exterieur sur un substrat semi-conducteur Granted FR2616965A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62154104A JPH0783053B2 (ja) 1987-06-19 1987-06-19 半導体装置

Publications (2)

Publication Number Publication Date
FR2616965A1 true FR2616965A1 (fr) 1988-12-23
FR2616965B1 FR2616965B1 (https=) 1994-04-22

Family

ID=15577008

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8808159A Granted FR2616965A1 (fr) 1987-06-19 1988-06-17 Interconnexion par montage en pont exterieur sur un substrat semi-conducteur

Country Status (4)

Country Link
US (1) US4924289A (https=)
JP (1) JPH0783053B2 (https=)
FR (1) FR2616965A1 (https=)
GB (1) GB2207808B (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0393635B1 (en) * 1989-04-21 1997-09-03 Nec Corporation Semiconductor device having multi-level wirings
US5019877A (en) * 1989-08-31 1991-05-28 Mitsubishi Denki Kabushiki Kaisha Field effect transistor
FR2653595B1 (fr) * 1989-10-25 1992-02-14 Valtronic France Circuit electronique a grille d'interconnexion.
JP3031966B2 (ja) * 1990-07-02 2000-04-10 株式会社東芝 集積回路装置
JPH05259159A (ja) * 1992-03-16 1993-10-08 Nec Ic Microcomput Syst Ltd 半導体集積回路装置内の配線形状
GB2273201B (en) * 1992-09-18 1996-07-10 Texas Instruments Ltd High reliablity contact scheme
JPH0722583A (ja) * 1992-12-15 1995-01-24 Internatl Business Mach Corp <Ibm> 多層回路装置
JPH08306774A (ja) * 1995-05-01 1996-11-22 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
CN1474452A (zh) * 1996-04-19 2004-02-11 ���µ�����ҵ��ʽ���� 半导体器件
JP2000269339A (ja) 1999-03-16 2000-09-29 Toshiba Corp 半導体集積回路装置とその配線配置方法
KR100697803B1 (ko) 2002-08-29 2007-03-20 시로 사카이 복수의 발광 소자를 갖는 발광 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2361745A1 (fr) * 1976-08-11 1978-03-10 Philips Nv Procede de fabrications de cabl
DE2852049A1 (de) * 1977-12-02 1979-06-07 Tokyo Shibaura Electric Co Fest- oder lesespeicher
US4673966A (en) * 1983-04-26 1987-06-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3921194A (en) * 1970-07-20 1975-11-18 Gen Electric Method and apparatus for storing and transferring information
JPS5154785A (https=) * 1974-11-08 1976-05-14 Nippon Electric Co
US3932226A (en) * 1974-12-06 1976-01-13 Rca Corporation Method of electrically interconnecting semiconductor elements
US4080722A (en) * 1976-03-22 1978-03-28 Rca Corporation Method of manufacturing semiconductor devices having a copper heat capacitor and/or copper heat sink
JPS5357781A (en) * 1976-11-05 1978-05-25 Toshiba Corp Semiconductor integrated circuit
US4651183A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation High density one device memory cell arrays

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2361745A1 (fr) * 1976-08-11 1978-03-10 Philips Nv Procede de fabrications de cabl
DE2852049A1 (de) * 1977-12-02 1979-06-07 Tokyo Shibaura Electric Co Fest- oder lesespeicher
US4673966A (en) * 1983-04-26 1987-06-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
INTERNATIONAL ELECTRON DEVICES MEETING' 83, Washington, DC, 5-7 décembre 1983, pages 542-545, IEEE, New York, US; R.M. GEFFKEN: "Multi-level metallurgy for master image structured logic" *

Also Published As

Publication number Publication date
GB2207808A (en) 1989-02-08
US4924289A (en) 1990-05-08
GB8814297D0 (en) 1988-07-20
JPS63318141A (ja) 1988-12-27
FR2616965B1 (https=) 1994-04-22
GB2207808B (en) 1990-07-11
JPH0783053B2 (ja) 1995-09-06

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