FR2586490B1 - Unite de traitement d'instruction de branchement - Google Patents

Unite de traitement d'instruction de branchement

Info

Publication number
FR2586490B1
FR2586490B1 FR8611998A FR8611998A FR2586490B1 FR 2586490 B1 FR2586490 B1 FR 2586490B1 FR 8611998 A FR8611998 A FR 8611998A FR 8611998 A FR8611998 A FR 8611998A FR 2586490 B1 FR2586490 B1 FR 2586490B1
Authority
FR
France
Prior art keywords
processing unit
instruction processing
connection instruction
connection
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR8611998A
Other languages
English (en)
Other versions
FR2586490A1 (fr
Inventor
Ishii Hideshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2586490A1 publication Critical patent/FR2586490A1/fr
Application granted granted Critical
Publication of FR2586490B1 publication Critical patent/FR2586490B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
FR8611998A 1985-08-22 1986-08-22 Unite de traitement d'instruction de branchement Expired - Fee Related FR2586490B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18532885 1985-08-22

Publications (2)

Publication Number Publication Date
FR2586490A1 FR2586490A1 (fr) 1987-02-27
FR2586490B1 true FR2586490B1 (fr) 1993-11-05

Family

ID=16168900

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8611998A Expired - Fee Related FR2586490B1 (fr) 1985-08-22 1986-08-22 Unite de traitement d'instruction de branchement

Country Status (3)

Country Link
US (1) US4882701A (fr)
JP (1) JPS6341932A (fr)
FR (1) FR2586490B1 (fr)

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JPS62180427A (ja) * 1986-02-03 1987-08-07 Nec Corp プログラム制御回路
US5101484A (en) * 1989-02-14 1992-03-31 Intel Corporation Method and apparatus for implementing an iterative program loop by comparing the loop decrement with the loop value
JPH0460720A (ja) * 1990-06-29 1992-02-26 Hitachi Ltd 条件分岐命令制御方式
US5313606A (en) * 1991-01-17 1994-05-17 Chips And Technologies, Inc. System for detecting boundary cross-over of instruction memory space using reduced number of address bits
US5303355A (en) * 1991-03-27 1994-04-12 Motorola, Inc. Pipelined data processor which conditionally executes a predetermined looping instruction in hardware
JPH07200292A (ja) * 1993-12-28 1995-08-04 Mitsubishi Electric Corp パイプライン式プロセッサ
US5404473A (en) * 1994-03-01 1995-04-04 Intel Corporation Apparatus and method for handling string operations in a pipelined processor
US5802346A (en) * 1995-06-02 1998-09-01 International Business Machines Corporation Method and system for minimizing the delay in executing branch-on-register instructions
US5909573A (en) * 1996-03-28 1999-06-01 Intel Corporation Method of branch prediction using loop counters
US5822602A (en) * 1996-07-23 1998-10-13 S3 Incorporated Pipelined processor for executing repeated string instructions by halting dispatch after comparision to pipeline capacity
WO1998036351A1 (fr) * 1997-02-17 1998-08-20 Hitachi, Ltd. Processeur de donnees
US7003543B2 (en) 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
US6937084B2 (en) 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US6728856B2 (en) 2001-06-01 2004-04-27 Microchip Technology Incorporated Modified Harvard architecture processor having program memory space mapped to data memory space
US7007172B2 (en) 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US6952711B2 (en) 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US6934728B2 (en) 2001-06-01 2005-08-23 Microchip Technology Incorporated Euclidean distance instructions
US6976158B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US7020788B2 (en) 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
US6975679B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US6552625B2 (en) 2001-06-01 2003-04-22 Microchip Technology Inc. Processor with pulse width modulation generator with fault input prioritization
US6985986B2 (en) 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
US6604169B2 (en) 2001-06-01 2003-08-05 Microchip Technology Incorporated Modulo addressing based on absolute offset
US20020184566A1 (en) 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US6601160B2 (en) 2001-06-01 2003-07-29 Microchip Technology Incorporated Dynamically reconfigurable data space
US7467178B2 (en) 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
US20040021483A1 (en) * 2001-09-28 2004-02-05 Brian Boles Functional pathway configuration at a system/IC interface
US6552567B1 (en) 2001-09-28 2003-04-22 Microchip Technology Incorporated Functional pathway configuration at a system/IC interface
US7721075B2 (en) * 2006-01-23 2010-05-18 Mips Technologies, Inc. Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses
US7721073B2 (en) * 2006-01-23 2010-05-18 Mips Technologies, Inc. Conditional branch execution in a processor having a data mover engine that associates register addresses with memory addresses
US7721074B2 (en) * 2006-01-23 2010-05-18 Mips Technologies, Inc. Conditional branch execution in a processor having a read-tie instruction and a data mover engine that associates register addresses with memory addresses
US8464030B2 (en) * 2010-04-09 2013-06-11 International Business Machines Corporation Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits
US8489865B1 (en) * 2010-04-15 2013-07-16 Lockheed Martin Corporation Device, system, and method for single thread command chaining instructions from multiple processor elements

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US3573854A (en) * 1968-12-04 1971-04-06 Texas Instruments Inc Look-ahead control for operation of program loops
US3593306A (en) * 1969-07-25 1971-07-13 Bell Telephone Labor Inc Apparatus for reducing memory fetches in program loops
BE789583A (fr) * 1971-10-01 1973-02-01 Sanders Associates Inc Appareil de controle de programme pour machine de traitement del'information
US4031521A (en) * 1971-10-15 1977-06-21 International Business Machines Corporation Multimode programmable machines
JPS549456B2 (fr) * 1972-07-05 1979-04-24
IT1000638B (it) * 1973-12-28 1976-04-10 Olivetti & Co Spa Calcolatore elettronico con dispo sitivo di deviazione dei micropro grammi
JPS522140A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Information processing apparatus
US4097920A (en) * 1976-12-13 1978-06-27 Rca Corporation Hardware control for repeating program loops in electronic computers
JPS5420385A (en) * 1977-07-15 1979-02-15 Mitsubishi Electric Corp Time switch
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4181942A (en) * 1978-03-31 1980-01-01 International Business Machines Corporation Program branching method and apparatus
JPS55146550A (en) * 1979-04-27 1980-11-14 Hitachi Ltd High speed branch controlling system
JPS5621239A (en) * 1979-07-27 1981-02-27 Fujitsu Ltd Processing system for branch instruction
JPS56129950A (en) * 1980-03-07 1981-10-12 Hitachi Ltd Information processor
JPS56149646A (en) * 1980-04-21 1981-11-19 Toshiba Corp Operation controller
JPS5734253A (en) * 1980-08-09 1982-02-24 Fujitsu Ltd Brunch instruction controlling circuit
US4370711A (en) * 1980-10-21 1983-01-25 Control Data Corporation Branch predictor using random access memory
US4430706A (en) * 1980-10-27 1984-02-07 Burroughs Corporation Branch prediction apparatus and method for a data processing system
US4462074A (en) * 1981-11-19 1984-07-24 Codex Corporation Do loop circuit
US4435756A (en) * 1981-12-03 1984-03-06 Burroughs Corporation Branch predicting computer
JPS58117050A (ja) * 1981-12-30 1983-07-12 Fujitsu Ltd デ−タシヨリソウチ
US4477872A (en) * 1982-01-15 1984-10-16 International Business Machines Corporation Decode history table for conditional branch instructions
US4463422A (en) * 1982-07-12 1984-07-31 Csp, Inc. Method of processing an iterative program loop
US4604691A (en) * 1982-09-07 1986-08-05 Nippon Electric Co., Ltd. Data processing system having branch instruction prefetching performance
JPS59146342A (ja) * 1983-02-09 1984-08-22 Nec Corp ル−プ制御方式
US4626988A (en) * 1983-03-07 1986-12-02 International Business Machines Corporation Instruction fetch look-aside buffer with loop mode control
JPS603750A (ja) * 1983-06-22 1985-01-10 Hitachi Ltd 計数分岐命令の制御方式
JPS6043751A (ja) * 1983-08-18 1985-03-08 Hitachi Ltd 情報処理装置
US4764861A (en) * 1984-02-08 1988-08-16 Nec Corporation Instruction fpefetching device with prediction of a branch destination for each branch count instruction
JPS60198640A (ja) * 1984-03-21 1985-10-08 Nec Corp パイプライン型情報処理装置
US4727483A (en) * 1984-08-15 1988-02-23 Tektronix, Inc. Loop control system for digital processing apparatus
JPS61273637A (ja) * 1985-05-30 1986-12-03 Nec Corp 情報処理装置
CA1285657C (fr) * 1986-01-29 1991-07-02 Douglas W. Clark Dispositif et methode d'execution d'instructions de branchement

Also Published As

Publication number Publication date
JPS6341932A (ja) 1988-02-23
US4882701A (en) 1989-11-21
FR2586490A1 (fr) 1987-02-27

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Legal Events

Date Code Title Description
ST Notification of lapse