FR2566581B1 - Procede de mise a la masse de dispositifs semi-conducteurs plans et de circuits integres, et produits ainsi obtenus - Google Patents

Procede de mise a la masse de dispositifs semi-conducteurs plans et de circuits integres, et produits ainsi obtenus

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Publication number
FR2566581B1
FR2566581B1 FR858509392A FR8509392A FR2566581B1 FR 2566581 B1 FR2566581 B1 FR 2566581B1 FR 858509392 A FR858509392 A FR 858509392A FR 8509392 A FR8509392 A FR 8509392A FR 2566581 B1 FR2566581 B1 FR 2566581B1
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FR
France
Prior art keywords
integrated circuits
contacts
products
semiconductor devices
planar semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR858509392A
Other languages
English (en)
Other versions
FR2566581A1 (fr
Inventor
Giampiero Donzelli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telettra Laboratori di Telefonia Elettronica e Radio SpA
Telettra SpA
Original Assignee
Telettra Telefonia Elettronica e Radio SpA
Telettra Laboratori di Telefonia Elettronica e Radio SpA
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Application filed by Telettra Telefonia Elettronica e Radio SpA, Telettra Laboratori di Telefonia Elettronica e Radio SpA filed Critical Telettra Telefonia Elettronica e Radio SpA
Publication of FR2566581A1 publication Critical patent/FR2566581A1/fr
Application granted granted Critical
Publication of FR2566581B1 publication Critical patent/FR2566581B1/fr
Expired legal-status Critical Current

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    • H01L21/746Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts for AIII-BV integrated circuits
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    • Y10S148/056Gallium arsenide
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/126Power FETs
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/135Removal of substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR858509392A 1984-06-22 1985-06-20 Procede de mise a la masse de dispositifs semi-conducteurs plans et de circuits integres, et produits ainsi obtenus Expired FR2566581B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT21553/84A IT1175541B (it) 1984-06-22 1984-06-22 Procedimento per la connessione a terra di dispositivi planari e circuiti integrati e prodotti cosi' ottenuti

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FR2566581A1 FR2566581A1 (fr) 1985-12-27
FR2566581B1 true FR2566581B1 (fr) 1989-12-29

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US (1) US4700467A (fr)
JP (1) JPS61111582A (fr)
DE (1) DE3522168C2 (fr)
ES (1) ES8609818A1 (fr)
FR (1) FR2566581B1 (fr)
GB (1) GB2161650B (fr)
IT (1) IT1175541B (fr)

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FR2684801B1 (fr) * 1991-12-06 1997-01-24 Picogiga Sa Procede de realisation de composants semiconducteurs, notamment sur gaas ou inp, avec recuperation du substrat par voie chimique.
US5268065A (en) * 1992-12-21 1993-12-07 Motorola, Inc. Method for thinning a semiconductor wafer
JP3287279B2 (ja) 1997-09-25 2002-06-04 日本電気株式会社 半導体チップ、および該半導体チップが実装された半導体装置
US7268081B2 (en) * 2000-11-02 2007-09-11 California Institute Of Technology Wafer-level transfer of membranes with gas-phase etching and wet etching methods
AU2002241597A1 (en) * 2000-11-02 2002-06-03 California Institute Of Technology Wafer-level transfer of membranes in semiconductor processing
KR100407472B1 (ko) * 2001-06-29 2003-11-28 삼성전자주식회사 트렌치가 형성된 상부 칩을 구비하는 칩 적층형 패키지소자 및 그 제조 방법

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FR2013735A1 (fr) * 1968-07-05 1970-04-10 Gen Electric Inf Ita
US3771219A (en) * 1970-02-05 1973-11-13 Sharp Kk Method for manufacturing semiconductor device
GB1602498A (en) * 1978-05-31 1981-11-11 Secr Defence Fet devices and their fabrication
GB1601059A (en) * 1978-05-31 1981-10-21 Secr Defence Fet devices and their fabrication
JPS55545A (en) * 1979-02-13 1980-01-05 Canon Inc Production of electrophotographic photoreceptor
IT8048031A0 (it) * 1979-04-09 1980-02-28 Raytheon Co Perfezionamento nei dispositivi a semiconduttore ad effetto di campo
JPS5749252A (en) * 1980-09-09 1982-03-23 Matsushita Electronics Corp Manufacture of semiconductor device
JPS5817626A (ja) * 1981-07-13 1983-02-01 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン 低温度ダイ取り付け方法

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ES8609818A1 (es) 1986-09-01
IT8421553A1 (it) 1985-12-22
ES544404A0 (es) 1986-09-01
JPS61111582A (ja) 1986-05-29
DE3522168C2 (de) 1994-05-11
GB8515479D0 (en) 1985-07-24
GB2161650B (en) 1988-07-13
US4700467A (en) 1987-10-20
DE3522168A1 (de) 1986-01-16
FR2566581A1 (fr) 1985-12-27
IT8421553A0 (it) 1984-06-22
IT1175541B (it) 1987-07-01
GB2161650A (en) 1986-01-15

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