FR2549274B1 - Cellule de memoire vive dynamique a rendement eleve et procede de fabrication - Google Patents

Cellule de memoire vive dynamique a rendement eleve et procede de fabrication

Info

Publication number
FR2549274B1
FR2549274B1 FR848410818A FR8410818A FR2549274B1 FR 2549274 B1 FR2549274 B1 FR 2549274B1 FR 848410818 A FR848410818 A FR 848410818A FR 8410818 A FR8410818 A FR 8410818A FR 2549274 B1 FR2549274 B1 FR 2549274B1
Authority
FR
France
Prior art keywords
manufacturing
memory cell
dynamic ram
ram memory
performance dynamic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR848410818A
Other languages
English (en)
Other versions
FR2549274A1 (fr
Inventor
Karl H K Yang
Andrew G Varadi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of FR2549274A1 publication Critical patent/FR2549274A1/fr
Application granted granted Critical
Publication of FR2549274B1 publication Critical patent/FR2549274B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
FR848410818A 1983-07-11 1984-07-06 Cellule de memoire vive dynamique a rendement eleve et procede de fabrication Expired - Fee Related FR2549274B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US51286883A 1983-07-11 1983-07-11

Publications (2)

Publication Number Publication Date
FR2549274A1 FR2549274A1 (fr) 1985-01-18
FR2549274B1 true FR2549274B1 (fr) 1990-01-26

Family

ID=24040938

Family Applications (1)

Application Number Title Priority Date Filing Date
FR848410818A Expired - Fee Related FR2549274B1 (fr) 1983-07-11 1984-07-06 Cellule de memoire vive dynamique a rendement eleve et procede de fabrication

Country Status (4)

Country Link
JP (1) JPS60149160A (fr)
DE (1) DE3425072A1 (fr)
FR (1) FR2549274B1 (fr)
GB (1) GB2143675B (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736437B2 (ja) * 1985-11-29 1995-04-19 株式会社日立製作所 半導体メモリの製造方法
US5061654A (en) * 1987-07-01 1991-10-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit having oxide regions with different thickness
JP2682021B2 (ja) * 1988-06-29 1997-11-26 富士通株式会社 半導体メモリ装置
KR920009748B1 (ko) * 1990-05-31 1992-10-22 삼성전자 주식회사 적층형 캐패시터셀의 구조 및 제조방법
JPH0497566A (ja) * 1990-08-15 1992-03-30 Nec Corp 半導体装置
US5036020A (en) * 1990-08-31 1991-07-30 Texas Instrument Incorporated Method of fabricating microelectronic device incorporating capacitor having lowered topographical profile
JP2773505B2 (ja) * 1991-12-27 1998-07-09 三菱電機株式会社 半導体装置およびその製造方法
JPH07142601A (ja) * 1993-11-15 1995-06-02 Nec Corp 半導体装置の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5491083A (en) * 1977-12-28 1979-07-19 Nec Corp Integrated-circuit device
JPS5621358A (en) * 1979-07-30 1981-02-27 Fujitsu Ltd Semiconductor memory device
JPS5793566A (en) * 1980-12-03 1982-06-10 Seiko Epson Corp Semiconductor device
JPS5854654A (ja) * 1981-09-28 1983-03-31 Nec Corp 半導体集積回路装置

Also Published As

Publication number Publication date
GB2143675B (en) 1987-05-07
DE3425072A1 (de) 1985-01-24
GB2143675A (en) 1985-02-13
GB8416781D0 (en) 1984-08-08
FR2549274A1 (fr) 1985-01-18
JPS60149160A (ja) 1985-08-06

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Legal Events

Date Code Title Description
ST Notification of lapse
ST Notification of lapse
ST Notification of lapse