FR2468185A1 - Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite - Google Patents

Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite Download PDF

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Publication number
FR2468185A1
FR2468185A1 FR8022291A FR8022291A FR2468185A1 FR 2468185 A1 FR2468185 A1 FR 2468185A1 FR 8022291 A FR8022291 A FR 8022291A FR 8022291 A FR8022291 A FR 8022291A FR 2468185 A1 FR2468185 A1 FR 2468185A1
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FR
France
Prior art keywords
lines
regions
contacts
substrate
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8022291A
Other languages
English (en)
French (fr)
Other versions
FR2468185B1 (enExample
Inventor
Joseph Shappir
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to FR8022291A priority Critical patent/FR2468185A1/fr
Publication of FR2468185A1 publication Critical patent/FR2468185A1/fr
Application granted granted Critical
Publication of FR2468185B1 publication Critical patent/FR2468185B1/fr
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
FR8022291A 1980-10-17 1980-10-17 Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite Granted FR2468185A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8022291A FR2468185A1 (fr) 1980-10-17 1980-10-17 Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8022291A FR2468185A1 (fr) 1980-10-17 1980-10-17 Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite

Publications (2)

Publication Number Publication Date
FR2468185A1 true FR2468185A1 (fr) 1981-04-30
FR2468185B1 FR2468185B1 (enExample) 1984-12-14

Family

ID=9247046

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8022291A Granted FR2468185A1 (fr) 1980-10-17 1980-10-17 Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite

Country Status (1)

Country Link
FR (1) FR2468185A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2543738A1 (fr) * 1983-03-31 1984-10-05 Ates Componenti Elettron Procede pour l'auto-alignement d'une double couche de silicium polycristallin, dans un dispositif a circuit integre, au moyen d'une operation d'oxydation
EP0144900A3 (en) * 1983-11-28 1986-10-08 Exel Microelectronics, Inc. An electrically programmable memory device and a method for making the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2296914A1 (fr) * 1974-12-30 1976-07-30 Intel Corp Dispositif de memoire a double-grille au silicium polycristallin
FR2330146A1 (fr) * 1975-10-29 1977-05-27 Intel Corp Procede de gravure a alignement automatique d'une couche double de silicium polycristallin
FR2375692A1 (fr) * 1976-12-27 1978-07-21 Texas Instruments Inc Memoire semi-conductrice a grilles flottantes, programmable electriquement
GB2004414A (en) * 1977-09-16 1979-03-28 Fairchild Camera Instr Co Insulated gate field-effect transistor read-only memory array
FR2403624A1 (fr) * 1977-09-16 1979-04-13 Fairchild Camera Instr Co Cellule de memoire inalterable a transistors a effet de champ a porte isolee
US4151021A (en) * 1977-01-26 1979-04-24 Texas Instruments Incorporated Method of making a high density floating gate electrically programmable ROM

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2296914A1 (fr) * 1974-12-30 1976-07-30 Intel Corp Dispositif de memoire a double-grille au silicium polycristallin
FR2330146A1 (fr) * 1975-10-29 1977-05-27 Intel Corp Procede de gravure a alignement automatique d'une couche double de silicium polycristallin
FR2375692A1 (fr) * 1976-12-27 1978-07-21 Texas Instruments Inc Memoire semi-conductrice a grilles flottantes, programmable electriquement
US4151021A (en) * 1977-01-26 1979-04-24 Texas Instruments Incorporated Method of making a high density floating gate electrically programmable ROM
GB2004414A (en) * 1977-09-16 1979-03-28 Fairchild Camera Instr Co Insulated gate field-effect transistor read-only memory array
FR2403624A1 (fr) * 1977-09-16 1979-04-13 Fairchild Camera Instr Co Cellule de memoire inalterable a transistors a effet de champ a porte isolee

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2543738A1 (fr) * 1983-03-31 1984-10-05 Ates Componenti Elettron Procede pour l'auto-alignement d'une double couche de silicium polycristallin, dans un dispositif a circuit integre, au moyen d'une operation d'oxydation
EP0144900A3 (en) * 1983-11-28 1986-10-08 Exel Microelectronics, Inc. An electrically programmable memory device and a method for making the same

Also Published As

Publication number Publication date
FR2468185B1 (enExample) 1984-12-14

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