FR2468185A1 - Programmable read only memory mfr. - forming two groups of conductive strips, mutually perpendicular and insulated and doped zones for memory cells using mos techniques - Google Patents

Abstract

The process is used for production of a programmable MOS semiconductor memory with a number of memory cells with floating gate electrodes. A first group of spaced, parallel polysilicon strips (18) are formed in a manner insulating them from the substrate (14). Between these strips are doped aligned elongated zones (22). A second group of strips (26) is formed in a manner insulated from the first strip and the doped zones. The second strips intersect the first and the doped zones in a tranverse direction. The first strips have regions aligned with the second strips and are etched to form the floating gate electrodes. These electrodes are formed each between two adjacent doped zones, formed underneath the second strips and insulated from them. The doped zones form bit-conducting zones with periodic arrangement of bit line contacts.

Description

 The present invention relates to the field of electrically programmable MOS read only memories (EPRON memories).

 Many electrically programmable read-only memories (vPROM memories) are commercially available. In many cases, these memories use floating-gate memory cells, the floating gates of which are loaded from the substrate by avalanche injection or channel injection. In general, these memory matrices are erased by exposing them to ultraviolet radiation. Examples of memory and floating gate memory cells are described in U.S. Patent Nos. 3,996,657; 4,094,012; 4,114,255 and 4,142,926.

 In a typical arrangement of these floating gate memory devices or cells, the cells are arranged in pairs. Each pair of cells is connected to an overlying metallic conductor via a metallic contact.

Half a contact per cell is therefore necessary. These contacts require a relatively large substrate area and, therefore, constitute one of the limitations in the manufacture of relatively high density dies. In addition, these metal contacts reduce the production yields of the memories, since they are generally more difficult to manufacture than other semiconductor elements of the matrix. As will be seen later, the present invention eliminates most of these metallic contacts and, for example, uses a single metallic contact for sixteen cells.

Some of the initial operations used in the method described here are analogous to the initial operations used in the manufacture of a mask-programmed read only memory as described in the US patent application. serial number 907.557 filed May 18, 1978 and entitled "MOS DOUBLE POLYSI
LICON READ-ONLY MEMORY AND CELL't (DEAD MEMORY AND CRQLUL # OF DnrMOiPr "ORTE IN DOUBLE POLYSILICON TO MOS) transferred to the Depositor. Other read only memory structures programmed by mask appearing are described in US Patent No. 4,095. 251.

 A method of fabricating an electrically programmable MOS memory array on a substrate is described below. In all that follows, the thin and narrow conductive tapes of the memory matrix will be designated for simplicity by the name of "lines". A first plurality of spaced parallel polysilicon lines isolated from the substrate are defined. Doped regions are then formed between these first lines in alignment with them. A second plurality of spaced parallel polysilicon lines, which are isolated from the first lines and the doped regions, are formed superimposed on the first lines and the doped regions. The second lines are essentially transverse to the first. The first lines are etched in alignment with the second lines so as to fade a plurality of floating grids from the first lines; each of these floating gates is arranged between two of the elongated doped regions and below one of the second lines. In this way, a plurality of electrically programmable floating gate dissidents are obtained, forming a high density mammary matrix.

 The invention will be better understood on reading the detailed description which follows and on examining the accompanying drawings, which represent, by way of non-limiting example, an embodiment.

On these drawings
Figure 1 is a partial plan view of a substrate, showing the initial operations of the process according to the invention. This view shows a plurality of first polysilicon lines formed on the substrate;
Figure 2 is an elevational view with cross section of the substrate and the lines of Figure 1, taken substantially along the line of section 2-2 of Figure 1;
Figure 3 shows the substrate of Figure 2 after the formation of second polysilicon lines on the substrate
Figure 4 is a plan view of the substrate of Figure 3
Figure 5 is a plan view showing the matrix of Figure 4 partially completed after etching operations used to define the floating grids;
Figure 6 is an elevational view with partial cross section of the substrate of Figure 5 taken substantially along the section lines 6-6 of Figure 5;
Figure 7 shows the matrix of Figure 5 after the formation of metallic lines above the doped regions
FIG. 8 is a plan view of part of a matrix manufactured according to the invention, which represents in particular the metal word lines and the staggered contacts used to interconnect these lines with the doped regions
Figure 9 is a plan view used to describe the presently preferred embodiment of the stepped contacts of Figure 8;
Figure 10 is a plan view of the intersection of one of the first and second polysilicon lines. This view is used to highlight the width of the channel regions
Figure II is an electrical diagram of part of the matrix manufactured according to the invention.

 A method of manufacturing an electrically programmable read-only memory (EPROM) with metal / oxide / semiconductor (MOS) devices with integrated circuit will be described below. In the following description of the presently preferred process, many specific details are indicated, such as specific layer thicknesses, etc. It will be clear to a specialist in this technique that the method according to the invention can be implemented without these specific details. In other cases, well-known processing operations have not been described, such as pickling, masking, the formation of protective layers, etc., so as not to overwhelm the description of the present invention by unnecessary details.

 Before describing the process according to the invention, it is good, to facilitate its understanding, to examine the resulting matrix in the form of an electrical diagram, Referring to Figure 11, it can be seen that the process according to the invention making a plurality of floating gate memory cells or devices such as devices 41, 42, 43 and 44. Each of these devices comprises a pair of spaced doped regions in the substrate, regions which it shares with other devices . Between these doped regions, above the channel region, is disposed a floating gate 45. These gates receive a charge from the substrate during programming as is well known. Control grids 44 are arranged above the floating grids.

The control grids are used during reading or detection, and are also used for programming as is well known. The operation and characteristics of the floating gate devices are substantially identical to what has been described in the above-cited patents.

 In the described method, the respective floating gates of all the devices are formed from first polysilicon lines which are parallel to the bit lines. The doped regions of the devices are formed substantially in alignment with these first lines. Word lines, such as lines 51 and 52, are made from a second layer of polysilicon. Overlying metal lines disposed above the doped regions (and in contact with them, as described below) form the bit lines of the matrix.

 By way of example, to read or program the device 41, appropriate signals are applied, as is well known, on line 51.

Reading takes place on bit lines 47 and 48 for device 41 (and for device 43). Programming potentials are also applied to these lines during programming. A plurality of cells can be read simultaneously, as is commonly done.

 To fabricate an entire memory on the same substrate using the high density memory array described, sense amplifiers are fabricated having a spacing substantially equal to the spacing of the bit lines. Similarly, decoders can be made with a spacing equal to, or substantially equal to, the spacing of the word lines. The fact that the second layer of polysilicon can pass over diffused substrate regions allows the realization of lesser spacing peripheral circuits. Well-known circuitry and mounting technology can be used to fabricate peripheral memory circuits, including sense amplifiers, decoders, programming circuits, buffers, etc.

 In the presently preferred method, the devices are n-channel devices produced on a p-type silicon substrate doped at a level of about 50 ohms-cm. Part of the substrate 14 is shown in Figure 2.

 In a particular preferred embodiment, no "frontal" field oxide is used in the matrix. On the other hand, such field oxides can be used in the peripheral circuits.

Thus, for example, the treatment described with reference to Figures 1 and 2 can be carried out after another treatment has been applied to the peripheral circuits, such as the growth of field oxides.

In the matrix (part of which is represented in the dashed line 12 of the
Figure 1), firstly by growth an oxide layer (silo2) on the substrate, then a polycrystalline silicon layer (polysilicon) is formed on the oxide layer. Next, a second oxide layer is formed on top of the poly silicon layer, and then a silicon nitride layer is formed on top of the second oxide layer. By well-known masking and etching operations, a plurality of lines (first lines of polysilicon 18) are defined on the substrate. As can clearly be seen in Figure 2, each of the lines 18 is separated from the substrate by an oxide line 16. Each line 18 is covered by an oxide line 19 and by a line made of silicon nitride 20. The oxide line 16 can have a thickness between 400 X and 1000, the polysilicon line 18 is approximately o 5000 thick, the oxide line 19 approximately 200 A thick and the Mine in silicon nitride 20 approximately 400 X thick . In general, a masking operation is first used to mask the layer of silicon nitride 20 so as to define the lines of silicon nitride 20 and then, by etching operations, lines 19 and 18. 16 is also engraved when a diffusion operation (as opposed to an ion implantation) is used to define the regions 22.

 Once the polysilicon lines 18 are defined, elongated doped regions 22 are formed in the substrate in alignment with the lines 18. A dopant consisting of phosphorus or arsenic can be used. Ordinary diffusion or ion implantation, or a combination of these two techniques, can be used. Preferably, a dopant level of 20 to 30 ohms / square is used.

The resulting structure is shown in Figures 1 and 2.

 Then, an oxide layer 24 is formed by growth above the matrix, as shown in Figure 3. The oxide does not grow below the silicon nitride element 20, so that this oxide covers the doped regions 22 and the side walls of the first polysilicon lines, but not the lines of silicon nitride 20.

 In some processes, it may be desirable to remove and then replace the oxide 19 lines and the silicon nitride? 0 lines before depositing a second layer of polysilicon. The reason why this has to be done in some cases is that the integrity of the oxide lines 19 and the silicon nitride lines 20 may deteriorate during the previous processing operations. (Silicon oxide and nitride are used as a dielectric in floating gate devices).

 A second layer of polysilicon is then deposited on the matrix; this layer can be about 6000 X thick. By an ordinary masking and etching operation, a plurality of spaced parallel polysilicon lines 26 is formed (second polysilicon lines). These lines, as shown in Figure 4, are substantially perpendicular to lines 18 and are located above the doped regions 22 and lines 18, from which they are isolated. The lines 26 are isolated from the regions doped by the oxide layer 24 and from the lines 18 by the oxide lines 19, and the lines made of silicon nitride 20.

 Then, the exposed silicon nitride and the underlying oxide covering the lines 18 are removed by etching. It should be noted that the silicon oxide and nitride situated above the lines 18 and below the lines 26 remain in place because the lines 26 prevent the etching corrosive from reaching these regions.

 The lines 18 are then etched in alignment with the lines 26. This eliminates the segments 18b from the lines 18 shown in Figure 4, since these segments are not protected by the lines 26. (An oxide layer is sometimes present above the lines 26 to prevent corrosil from attacking these lines. This oxide layer may be the same as that used in the masking and etching operations ensuring the formation of the lines 26). In the presently preferred embodiment, a self-aligning etching method is used to ensure the alignment of the segments 18a of the lines 18 with the edges of the lines 26. This etching method is described in the US patent. no 4,142,926.

Referring to Figure 5, it can be seen that the resulting structure now includes lines 26 with line segments 18a formed from lines 18 disposed below lines 26 between the scattered regions 22. Line segments 18a form the floating grids of memory devices. As can be clearly seen in Figure 6, the resulting structure includes the overlying lines 26 isolated from the floating gorilla 18a by the silicon nitride element 20a (formed from line 20) and by the element in oxide 19a (formed from the line in oxide 19). The oxide layer 16 separates the floating gate 18a from the channel defined between the elongated regions 22. The device shown in the
Figure 6 is a floating gate memory device corresponding to devices 41, 42, 43 and 44 of Figure 11.

 Metallic lines (or other conductive lines) are then formed above the regions 22. In the presently preferred embodiment, aluminum lines 30 are produced by well known operations above the regions 22.

Periodically, along the lines 30, outgoing contacts formed, as shown in FIG. 8 between the lines 50 and the underlying substrate regions 22.

These contacts, as described below, can be metallic contacts or buried contacts spaced periodically along the lines 30, between groups of cells (for example between series of sixteen lines 26).

 The substrate regions located below the removed line segments 18, shown as regions 28a in Figure 7, are of the same type of conductivity and have the same resistivity as the substrate. "Breakdowns" between regions 22 can occur in regions 28a, particularly when relatively high programming potentials are used. For this reason, the entire matrix is subjected to boron implantation to implant the regions 28a. This layout defines field barriers between the regions 22, except, of course, in the channel region of the memory devices. An implantation at a level of 1-3 x 1 o12 atoms / cm2 is considered sufficient.

Alternatively, regions 28a can be field oxide regions. In this alternative embodiment, the field oxide regions are formed previously from the definition of lines 18 of the
Figure 1. These field oxide regions can be formed, for example, during "front end" operations when defining other field oxide regions in peripheral circuits. These field oxide regions (as opposed to boron implantation) provide better breakdown resistance characteristics; however, more area is required when using these field oxide regions, mainly due to the problem of bird beak (# ird-beak) and misalignments between successive processing operations.

We will now refer to the
Figure 8, on which a part of the matrix is again represented, but this time without the lines 26 for the sake of simplicity. As described above, after defining the aluminum lines 30, contacts are formed periodically along these lines. These contacts extend down to the underlying regions 22. These contacts, together with the metallic lines 30, improve the conductivity along the doped regions 22. The contacts made with the usual technology are slightly larger than the spacing of lines 26 and 30, and therefore cannot be placed in alignment.

This is why the contacts are staggered. For example, the contacts 37a are arranged on a determined horizontal line while the contacts 37b are arranged on another horizontal line. Similarly, the contacts 38a are arranged on a certain horizontal line and the contacts 38b on another. As described above, the contacts 37 and 38 can be separated by a group of cells, for example the pmseize c11ws, that is to say sixteen lines 26 26seni ^ of ~~ s available between the contacts 37 and 38. In the contact regions, no cell is manufactured and, therefore, lines 26 are absent. Ordinary metal contacts can be used to form contacts 37 and 38.

In the presently preferred embodiment, instead of using direct metallic contacts, buried contacts are used, while the metallic lines are in contact with pads formed from the first layer of polysilicon. A description of a method of manufacturing these contacts including a discussion of the formation of field oxide regions is found in the patent.
US. no 4.033.026. Referring to Figure 9, it can be seen that during front-end memory processing, field oxide regions 32 are formed in the stepped contact regions. In the example shown, these regions are adjacent to the lines 18 subsequently formed from the first layer of polysilicon. The first layer of polysilicon is also used to define the contacts 34, which are in direct contact with the substrate (or with a doped region of the substrate). Metal contacts are then used which extend between the metal lines and the polysilicon contacts 34. In this way, it is not necessary to provide metal contacts extending between the metal line and the substrate. Here again, in the case of FIG. 8, the contacts are staggered.

 It is also possible to stagger the contacts with other configurations. For example, the contacts 37b could be spaced from the contacts 37a with eight rows of cells between the contacts 37a and 37b With this diEposilicn, the contacts 38b ent es; EIGfs c # ottats 38a by eight rows of cells. Thus, a line of contacts would appear every eight rows of cells in the matrix and each line of contacts would extend from alternating metal lines.

 FIG. 10 shows a configuration of lines 18 which improves the performance of the memory devices as well as the characteristics of resistance to breakdown through the regions 22. The lines 18 are slightly narrower in the channel regions of the devices, that is, below lines 26. This is indicated by the dimension "a". The rest of lines 18, mainly between lines 26, is slightly wider, as indicated by dimension b. The dimension "a", since it is slightly narrower, facilitates the programming of floating grids thanks to the narrow channel. Furthermore, the greater distance between the regions 22 (where no active device is present) increases the potential for breakdown. For a typical current treatment technology, "a" can be included in the range from 2.5 11 to 4.0 ~ u and "b" between 4.0 Eu and 6.0 p.

 In typical commercial manufacturing of EPROM memory cells where one half contact is used per cell, a substrate area of approximately (4.57 mm2) is required for an EPROM memory of 64 K. Using design rules a little more imperative, these cells can be reduced to approximately (3.60 mm2). Cells manufactured by the method according to the invention without the implanted field barriers require approximately 9 11 x 9 p of surface area of substrate, which corresponds to a matrix area of approximately (3.20 mm 2). This area can be reduced to approximately (3.02 mm2) with conventional technology depending on masking, etching techniques, etc.

that are used. When using field oxide isolation between cells with current technology, the matrix areas are in the range of (3.20 mm2) to (3.66 mm2) for an EPROM of 64 K. Thus, when using the method described here, a considerably smaller matrix area is necessary, even if one takes account of the periodic contacts along the metal lines, such as the contacts 37 and 38 of FIG. 8. This reduction in the area of the matrix is obtained mainly thanks to the reduction in the number of contacts in the matrix.

 Although in the presently preferred embodiment, as shown clearly in Figure 6, the oxide food 19a and the silicon nitride element 20a are used to separate line 26 from the floating gate 18a, these two elements may not necessarily be dependent on the process used, etc. For example, one can use a thicker oxide element 19a alone, or else only a silicon nitride element.

 It will easily be understood that, although only the production of a small number of cells has been shown in the drawings, in fact, as is generally the case, a large matrix of cells is simultaneously produced. In addition, during the fabrication of the cell matrix, another photolithographic fabrication, mainly in the peripheral circuits, can be carried out simultaneously. For example, when defining lines 18 from the first layer of polysilicon, grids field effect transistors can be simultaneously formed in the peripheral circuits A masking operation and related operations make it possible to produce the growth of a thick oxide on the first polysilicon elements in the peripheral circuits, together with the growth of the thick oxide above the doped substrate regions of the matrix.

Thus, during the etching of the first polysilicon layer in the matrix (which follows the etching of the second polysilicon layer), the elements of the first polysilicon layer of the peripheral circuits are not attacked. The second polysilicon layer of the peripheral circuits can be used for additional interconnections.

 It can be seen that a method of manufacturing a high density electrically programmable read-only memory array has been described above. The number of contacts used in the matrix is considerably reduced compared to the prior art, which allows higher densities in addition to better yields. Contrary to what happens in other prior art floating gate device forming methods, the second polysilicon lines intersect the doped regions of the substrate, which facilitates a denser configuration.

Claims (11)

 1. A method of manufacturing an electrically programmable memory array with metal / oxide / semiconductor devices on a substrate, said method comprising the operations consisting in: forming a first plurality of spaced parallel polysilicon lines (18), isolated from said substrate; doping elongated regions (22) in said substrate between said first lines, in alignment therewith to form a second plurality of spaced parallel polysilicon lines (26) isolated from said first lines and said doped regions, said second lines being essentially transverse to the first and overlying them and to said doped regions and to etching (18b) said first lines in alignment with said second polysilicon lines, so as to form a plurality of floating grids from said first lines, each of said grids floats (18a) being disposed between two of said doped regions (22) and being isolated from and disposed below one of said second lines (26) whereby a plurality of floating gate memory devices are obtained electrically programmable forming a high density memory array.  2. Method according to claim 1, characterized in that it comprises the formation of a third plurality (30) of conductive lines each parallel to one of said doped regions above it, with contacts between said third lines (30) and their respective underlying doped regions (22), said contacts being formed between groups of said second lines.  3. Method according to claim 2, characterized in that said first lines (18) are formed with a line of overlying silicon nitride (20a).  4. Method according to claim 2, characterized in that it comprises an operation consisting in forming isolation regions (28a) in the substrate, in the regions limited by the floating grids on opposite first sides and by the third lines on opposite second sides.  5. Method according to claim 4, characterized in that said isolation regions (28a) are formed by ion implantation.  6. Method according to claim 2, characterized in that it comprises the formation of isolation regions (28a) in field oxide bounded by the floating grids on first opposite sides and by the third lines on second opposite sides.  7. Method for manufacturing an electrically programmable memory array with metal / oxide / semiconductor devices on a p-type silicon substrate, said method being characterized in that it comprises the operations consisting in: forming a first plurality spaced parallel polysilicon lines (18) isolated from said substrate by an oxide layer; doping elongated regions (22) in said substrate between said first lines with an n-type dopant, in alignment with said first lines; forming an oxide layer (19, 24) over said elongated doped lines; forming a second plurality of spaced parallel polysilicon lines (26), isolated from said first lines and said doped regions, said second lines being essentially transverse to the first and overlying them and to said doped regions; etching (18b) said first lines in alignment with said second polysilicon lines so as to form a plurality of floating gates from said first lines, each of said floating gates (18a) being disposed between two of said doped regions and being isolated from one of said second lines and disposed below it; forming contacts (37, 38) with said doped region, these contacts being formed between groups of the second lines and forming a third plurality (30) of conductive lines each parallel to one of the doped regions, above the latter, in contact with the aforementioned contacts, whereby a plurality of electrically programmable floating gate memory devices is obtained, forming a high density memory array.  8. Method according to claim 7, characterized in that said contacts (37, 38) are staggered along lines substantially parallel to said second lines (26).  9. Method according to claim 7, characterized in that isolation regions (28a) are formed, regions which are limited by said floating grids (18a) on opposite first sides and by said third lines (30) on second opposite sides.  10. The method of claim 9, characterized in that said isolation regions are formed by ion implantation.  11. Method according to claim 9, characterized in that said isolation regions are formed by a field oxidation operation.