FR2463509B1 - Procede de fabrication de dispositifs semi-conducteurs et dispositifs obtenus par ce procede - Google Patents

Procede de fabrication de dispositifs semi-conducteurs et dispositifs obtenus par ce procede

Info

Publication number
FR2463509B1
FR2463509B1 FR8017774A FR8017774A FR2463509B1 FR 2463509 B1 FR2463509 B1 FR 2463509B1 FR 8017774 A FR8017774 A FR 8017774A FR 8017774 A FR8017774 A FR 8017774A FR 2463509 B1 FR2463509 B1 FR 2463509B1
Authority
FR
France
Prior art keywords
devices
manufacturing semiconductor
semiconductor devices
devices obtained
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8017774A
Other languages
English (en)
Other versions
FR2463509A1 (fr
Inventor
Yoshihiko Mizushima
Akitsu Takeda
Akira Yoshikawa
Osamu Ochi
Tomoko Hisaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP54103051A external-priority patent/JPS5855654B2/ja
Priority claimed from JP54103052A external-priority patent/JPS603772B2/ja
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of FR2463509A1 publication Critical patent/FR2463509A1/fr
Application granted granted Critical
Publication of FR2463509B1 publication Critical patent/FR2463509B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/0042—Photosensitive materials with inorganic or organometallic light-sensitive compounds not otherwise provided for, e.g. inorganic resists
    • G03F7/0044—Photosensitive materials with inorganic or organometallic light-sensitive compounds not otherwise provided for, e.g. inorganic resists involving an interaction between the metallic and non-metallic component, e.g. photodope systems
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/93—Ternary or quaternary semiconductor comprised of elements from three different groups, e.g. I-III-V

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
FR8017774A 1979-08-13 1980-08-12 Procede de fabrication de dispositifs semi-conducteurs et dispositifs obtenus par ce procede Expired FR2463509B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP54103051A JPS5855654B2 (ja) 1979-08-13 1979-08-13 半導体装置の製法
JP54103052A JPS603772B2 (ja) 1979-08-13 1979-08-13 半導体装置の製法

Publications (2)

Publication Number Publication Date
FR2463509A1 FR2463509A1 (fr) 1981-02-20
FR2463509B1 true FR2463509B1 (fr) 1986-05-02

Family

ID=26443711

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8017774A Expired FR2463509B1 (fr) 1979-08-13 1980-08-12 Procede de fabrication de dispositifs semi-conducteurs et dispositifs obtenus par ce procede

Country Status (3)

Country Link
US (1) US4350541A (fr)
DE (1) DE3030660C2 (fr)
FR (1) FR2463509B1 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4398964A (en) * 1981-12-10 1983-08-16 Signetics Corporation Method of forming ion implants self-aligned with a cut
FI95816C (fi) * 1989-05-04 1996-03-25 Ad Tech Holdings Ltd Antimikrobinen esine ja menetelmä sen valmistamiseksi
JPH04199507A (ja) * 1990-11-28 1992-07-20 Mitsubishi Electric Corp ３―Ｖ族化合物半導体へのｎ型不純物固相拡散方法
JP3160205B2 (ja) * 1996-09-02 2001-04-25 科学技術振興事業団 半導体装置の製造方法およびその製造装置
US5998066A (en) * 1997-05-16 1999-12-07 Aerial Imaging Corporation Gray scale mask and depth pattern transfer technique using inorganic chalcogenide glass
KR100308133B1 (ko) * 1999-01-12 2001-09-26 김영환 듀얼 게이트 모스 트랜지스터 제조방법
US20020168586A1 (en) * 2001-05-10 2002-11-14 Shih-Che Lo Near field optical disk
US6709958B2 (en) * 2001-08-30 2004-03-23 Micron Technology, Inc. Integrated circuit device and fabrication using metal-doped chalcogenide materials
US20030143782A1 (en) 2002-01-31 2003-07-31 Gilton Terry L. Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures
DE10217610B4 (de) * 2002-04-19 2005-11-03 Infineon Technologies Ag Metall-Halbleiter-Kontakt, Halbleiterbauelement, integrierte Schaltungsanordnung und Verfahren
US20060045974A1 (en) * 2004-08-25 2006-03-02 Campbell Kristy A Wet chemical method to form silver-rich silver-selenide
US20060127821A1 (en) * 2004-12-09 2006-06-15 Sanyo Electric Co., Ltd. Method of forming a photoresist pattern
KR100704380B1 (ko) * 2005-12-06 2007-04-09 한국전자통신연구원 반도체 소자 제조 방법
US8962460B2 (en) * 2011-04-26 2015-02-24 Micron Technology, Inc. Methods of selectively forming metal-doped chalcogenide materials, methods of selectively doping chalcogenide materials, and methods of forming semiconductor device structures including same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3532563A (en) * 1968-03-19 1970-10-06 Milton Genser Doping of semiconductor surfaces
DE2211017A1 (de) * 1971-03-09 1972-10-05 Motorola, Inc., Franklin Park, 111. Lichtempfindlicher, organischer, glasartiger Film
US3801384A (en) * 1971-04-15 1974-04-02 Monsanto Co Fabrication of semiconductor devices
GB1529037A (en) * 1976-06-08 1978-10-18 Nippon Telegraph & Telephone Image-forming materials having a radiation sensitive chalcogenide coating and a method of forming images with such materials
DE2754833A1 (de) * 1977-12-09 1979-06-13 Ibm Deutschland Phosphordiffusionsverfahren fuer halbleiteranwendungen

Also Published As

Publication number Publication date
FR2463509A1 (fr) 1981-02-20
DE3030660C2 (de) 1985-10-03
DE3030660A1 (de) 1981-03-26
US4350541A (en) 1982-09-21

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Legal Events

Date Code Title Description
TP Transmission of property
ST Notification of lapse