FR2446515A1 - Dispositif de controle a multiprocesseur pour chassis d'unites de branchement - Google Patents

Dispositif de controle a multiprocesseur pour chassis d'unites de branchement

Info

Publication number
FR2446515A1
FR2446515A1 FR8000610A FR8000610A FR2446515A1 FR 2446515 A1 FR2446515 A1 FR 2446515A1 FR 8000610 A FR8000610 A FR 8000610A FR 8000610 A FR8000610 A FR 8000610A FR 2446515 A1 FR2446515 A1 FR 2446515A1
Authority
FR
France
Prior art keywords
bus
microprocessor
register
data
address register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8000610A
Other languages
English (en)
Other versions
FR2446515B3 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAZA AVTOMATIZACIA NAUCHNIA EX
Original Assignee
BAZA AVTOMATIZACIA NAUCHNIA EX
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BAZA AVTOMATIZACIA NAUCHNIA EX filed Critical BAZA AVTOMATIZACIA NAUCHNIA EX
Publication of FR2446515A1 publication Critical patent/FR2446515A1/fr
Application granted granted Critical
Publication of FR2446515B3 publication Critical patent/FR2446515B3/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)

Abstract

Ce dispositif qui comprend un microprocesseur de commande 1 avec une mémoire 2, tout deux etant respectivement connectés bidirectionnellement au bus 3 du microprocesseur, se caractérise en ce que le processeur de commande du canal des données 4 est connecté à une mémoire-programme 5, à un multiplexeur 6, aux adresses du registre d'adresse 7 de la mémoire-programme 5, à un processeur de traitement des interruptions 9, à un registre d'adresses de données 10, à un registre de données et au bus 3 du microprocesseur, en ce que la mémoire-programme 5 est connectée au bus 3 du microprocesseur, au registre des positions 8, au multiplexeur 6 et au registre d'adresses de données; et en ce que le multiplexeur 6 est connecté au bus du microprocesseur et à un registre d'adresse 7 de la mémoire-programme, qui est relié au bus 3 du microprocesseur, tandis que le registre des positions 8 est connecté au bus << CAMAC >> 12 et que le processeur de traitement des interruptions 9, le registre des adresses de données 10 et le registre des données sont connectés au bus 3 du microprocesseur ainsi qu'au bus << CAMAC >> 12. Ce dispositif sert en particulier au contrôle des châssis d'unités de branchement appelés également << crates >>.
FR8000610A 1979-01-11 1980-01-11 Dispositif de controle a multiprocesseur pour chassis d'unites de branchement Granted FR2446515A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BG7942038A BG29103A1 (en) 1979-01-11 1979-01-11 Multiprocessor cratecontroler

Publications (2)

Publication Number Publication Date
FR2446515A1 true FR2446515A1 (fr) 1980-08-08
FR2446515B3 FR2446515B3 (fr) 1981-11-20

Family

ID=3905501

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8000610A Granted FR2446515A1 (fr) 1979-01-11 1980-01-11 Dispositif de controle a multiprocesseur pour chassis d'unites de branchement

Country Status (7)

Country Link
US (1) US4503498A (fr)
BG (1) BG29103A1 (fr)
DD (1) DD161126A3 (fr)
DE (1) DE3000872A1 (fr)
FR (1) FR2446515A1 (fr)
GB (1) GB2039395B (fr)
SU (1) SU1072054A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4626985A (en) * 1982-12-30 1986-12-02 Thomson Components - Mostek Corporation Single-chip microcomputer with internal time-multiplexed address/data/interrupt bus
US5010476A (en) * 1986-06-20 1991-04-23 International Business Machines Corporation Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units
US5371874A (en) * 1989-01-27 1994-12-06 Digital Equipment Corporation Write-read/write-pass memory subsystem cycle
US5423008A (en) * 1992-08-03 1995-06-06 Silicon Graphics, Inc. Apparatus and method for detecting the activities of a plurality of processors on a shared bus
JP3506582B2 (ja) * 1997-03-28 2004-03-15 沖電気工業株式会社 電子マネーシステム

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4377000A (en) * 1980-05-05 1983-03-15 Westinghouse Electric Corp. Automatic fault detection and recovery system which provides stability and continuity of operation in an industrial multiprocessor control

Also Published As

Publication number Publication date
BG29103A1 (en) 1980-09-15
SU1072054A1 (ru) 1984-02-07
DD161126A3 (de) 1985-01-09
GB2039395B (en) 1983-07-20
GB2039395A (en) 1980-08-06
US4503498A (en) 1985-03-05
FR2446515B3 (fr) 1981-11-20
DE3000872A1 (de) 1980-07-24

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