FR2413717A1 - Dispositif de traitement d'interruptions pour un ordinateur - Google Patents
Dispositif de traitement d'interruptions pour un ordinateurInfo
- Publication number
- FR2413717A1 FR2413717A1 FR7836907A FR7836907A FR2413717A1 FR 2413717 A1 FR2413717 A1 FR 2413717A1 FR 7836907 A FR7836907 A FR 7836907A FR 7836907 A FR7836907 A FR 7836907A FR 2413717 A1 FR2413717 A1 FR 2413717A1
- Authority
- FR
- France
- Prior art keywords
- interruption processing
- processing device
- encoder
- computer
- interruption
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
L'INVENTION CONCERNE L'INFORMATIQUE. UN DISPOSITIF DE TRAITEMENT D'INTERRUPTIONS COMPREND NOTAMMENT UN CODEUR DE PRIORITE 7 QUI RECOIT LES SIGNAUX DE DEMANDE D'INTERRUPTION, ET QUI DETERMINE LE SIGNAL DE DEMANDE ACTIF QUI A LA PRIORITE LA PLUS ELEVEE. LE CODEUR 7 ATTAQUE DES MEMOIRES MORTES 5 ET 6 QUI FOURNISSENT UNE ADRESSE DE REMPLACEMENT QUI EST L'ADRESSE DE DEPART DU SOUS-PROGRAMME DE TRAITEMENT DE L'INTERRUPTION QUI EST SELECTIONNEE PAR LE CODEUR 7. APPLICATION AUX MICRO-ORDINATEURS.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US86579677A | 1977-12-30 | 1977-12-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2413717A1 true FR2413717A1 (fr) | 1979-07-27 |
FR2413717B1 FR2413717B1 (fr) | 1986-03-28 |
Family
ID=25346246
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7836907A Expired FR2413717B1 (fr) | 1977-12-30 | 1978-12-29 | Dispositif de traitement d'interruptions pour un ordinateur |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS5819094B2 (fr) |
DE (1) | DE2856768C2 (fr) |
FR (1) | FR2413717B1 (fr) |
GB (1) | GB2012082B (fr) |
IT (1) | IT1192603B (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0167140A2 (fr) * | 1984-07-05 | 1986-01-08 | Nec Corporation | Circuit de commande d'interruptions |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4271468A (en) * | 1979-11-06 | 1981-06-02 | International Business Machines Corp. | Multiprocessor mechanism for handling channel interrupts |
JPS61143852A (ja) * | 1984-12-17 | 1986-07-01 | Toshiba Corp | 割込みベクトル保護方法 |
KR100317237B1 (ko) * | 1999-10-01 | 2001-12-22 | 윤종용 | 유사 벡터 방식의 인터럽트 컨트롤러 및 그것의 인터럽트 처리 방법 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50106541A (fr) * | 1974-01-29 | 1975-08-22 | ||
JPS51233A (fr) * | 1974-06-19 | 1976-01-05 | Nippon Electric Co | |
JPS5428260B2 (fr) * | 1974-09-02 | 1979-09-14 | ||
JPS5232647A (en) * | 1975-09-08 | 1977-03-12 | Mitsui Eng & Shipbuild Co Ltd | Interruption system of electronic computer |
US4090238A (en) * | 1976-10-04 | 1978-05-16 | Rca Corporation | Priority vectored interrupt using direct memory access |
-
1978
- 1978-12-15 IT IT30897/78A patent/IT1192603B/it active
- 1978-12-19 GB GB7849060A patent/GB2012082B/en not_active Expired
- 1978-12-26 JP JP53164534A patent/JPS5819094B2/ja not_active Expired
- 1978-12-29 DE DE2856768A patent/DE2856768C2/de not_active Expired
- 1978-12-29 FR FR7836907A patent/FR2413717B1/fr not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0167140A2 (fr) * | 1984-07-05 | 1986-01-08 | Nec Corporation | Circuit de commande d'interruptions |
EP0167140A3 (en) * | 1984-07-05 | 1986-09-03 | Nec Corporation | Interruption control circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS54103645A (en) | 1979-08-15 |
DE2856768A1 (de) | 1979-07-05 |
IT7830897A0 (it) | 1978-12-15 |
DE2856768C2 (de) | 1984-02-09 |
FR2413717B1 (fr) | 1986-03-28 |
JPS5819094B2 (ja) | 1983-04-16 |
IT1192603B (it) | 1988-04-20 |
GB2012082B (en) | 1982-06-09 |
GB2012082A (en) | 1979-07-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |