DD161126A3 - Mehrprozessor-cratecontroller - Google Patents

Mehrprozessor-cratecontroller

Info

Publication number
DD161126A3
DD161126A3 DD80218359A DD21835980A DD161126A3 DD 161126 A3 DD161126 A3 DD 161126A3 DD 80218359 A DD80218359 A DD 80218359A DD 21835980 A DD21835980 A DD 21835980A DD 161126 A3 DD161126 A3 DD 161126A3
Authority
DD
German Democratic Republic
Prior art keywords
cratecontroller
processor
processor cratecontroller
Prior art date
Application number
DD80218359A
Other languages
German (de)
English (en)
Inventor
Ljubomir J Antonov
Alexander M Trenev
Angel M Angelov
Kostadin D Janev
Original Assignee
Basa Sa Avtomatisazia Na Nauts
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Basa Sa Avtomatisazia Na Nauts filed Critical Basa Sa Avtomatisazia Na Nauts
Publication of DD161126A3 publication Critical patent/DD161126A3/xx

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
DD80218359A 1979-01-11 1980-01-04 Mehrprozessor-cratecontroller DD161126A3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BG7942038A BG29103A1 (en) 1979-01-11 1979-01-11 Multiprocessor cratecontroler

Publications (1)

Publication Number Publication Date
DD161126A3 true DD161126A3 (de) 1985-01-09

Family

ID=3905501

Family Applications (1)

Application Number Title Priority Date Filing Date
DD80218359A DD161126A3 (de) 1979-01-11 1980-01-04 Mehrprozessor-cratecontroller

Country Status (7)

Country Link
US (1) US4503498A (xx)
BG (1) BG29103A1 (xx)
DD (1) DD161126A3 (xx)
DE (1) DE3000872A1 (xx)
FR (1) FR2446515A1 (xx)
GB (1) GB2039395B (xx)
SU (1) SU1072054A1 (xx)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4626985A (en) * 1982-12-30 1986-12-02 Thomson Components - Mostek Corporation Single-chip microcomputer with internal time-multiplexed address/data/interrupt bus
US5010476A (en) * 1986-06-20 1991-04-23 International Business Machines Corporation Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units
US5371874A (en) * 1989-01-27 1994-12-06 Digital Equipment Corporation Write-read/write-pass memory subsystem cycle
US5423008A (en) * 1992-08-03 1995-06-06 Silicon Graphics, Inc. Apparatus and method for detecting the activities of a plurality of processors on a shared bus
JP3506582B2 (ja) * 1997-03-28 2004-03-15 沖電気工業株式会社 電子マネーシステム

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4377000A (en) * 1980-05-05 1983-03-15 Westinghouse Electric Corp. Automatic fault detection and recovery system which provides stability and continuity of operation in an industrial multiprocessor control

Also Published As

Publication number Publication date
BG29103A1 (en) 1980-09-15
DE3000872A1 (de) 1980-07-24
FR2446515B3 (xx) 1981-11-20
GB2039395A (en) 1980-08-06
SU1072054A1 (ru) 1984-02-07
US4503498A (en) 1985-03-05
GB2039395B (en) 1983-07-20
FR2446515A1 (fr) 1980-08-08

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Legal Events

Date Code Title Description
ENJ Ceased due to non-payment of renewal fee
ENJ Ceased due to non-payment of renewal fee