FR2388342A1 - Systeme informatique a cadence d'horloge variable - Google Patents

Systeme informatique a cadence d'horloge variable

Info

Publication number
FR2388342A1
FR2388342A1 FR7811743A FR7811743A FR2388342A1 FR 2388342 A1 FR2388342 A1 FR 2388342A1 FR 7811743 A FR7811743 A FR 7811743A FR 7811743 A FR7811743 A FR 7811743A FR 2388342 A1 FR2388342 A1 FR 2388342A1
Authority
FR
France
Prior art keywords
computer system
clock rate
memory units
variable clock
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7811743A
Other languages
English (en)
Other versions
FR2388342B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Publication of FR2388342A1 publication Critical patent/FR2388342A1/fr
Application granted granted Critical
Publication of FR2388342B1 publication Critical patent/FR2388342B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Abstract

L'invention concerne les systèmes informatiques. Un système informatique comprend une unité de commande 1, une horloge 4 et des unités de mémoire 2. Chaque unité de mémoire peut être d'un type lent ou d'un type rapide, et la borne X des unités de mémoire de type lent est connectée à la masse, tandis que celle des unités de mémoire de type rapide est en circuit ouvert. La cadence des signaux que l'horloge 4 applique à l'unité de commande 1 est automatiquement com mandée par l'état de la ligne 6 reliée aux bornes X. Application aux systèmes informatiques fonctionnant en mi croprogrammation.
FR7811743A 1977-04-20 1978-04-20 Systeme informatique a cadence d'horloge variable Expired FR2388342B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB16380/77A GB1561961A (en) 1977-04-20 1977-04-20 Data processing units

Publications (2)

Publication Number Publication Date
FR2388342A1 true FR2388342A1 (fr) 1978-11-17
FR2388342B1 FR2388342B1 (fr) 1985-11-22

Family

ID=10076279

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7811743A Expired FR2388342B1 (fr) 1977-04-20 1978-04-20 Systeme informatique a cadence d'horloge variable

Country Status (9)

Country Link
US (1) US4217637A (fr)
JP (1) JPS5439538A (fr)
AU (1) AU513884B2 (fr)
DE (1) DE2815283C3 (fr)
FR (1) FR2388342B1 (fr)
GB (1) GB1561961A (fr)
NL (1) NL176715C (fr)
PL (1) PL116378B1 (fr)
ZA (1) ZA782047B (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0212636A2 (fr) * 1985-08-21 1987-03-04 Nec Corporation Circuit de commande de l'état d'un bus
EP0386935A2 (fr) * 1989-03-08 1990-09-12 Canon Kabushiki Kaisha Appareil capable de varier le nombre d'états d'attente pour accès
EP0497441A2 (fr) * 1991-01-28 1992-08-05 Advanced Micro Devices, Inc. Système amélioré de chronogramme synchrone pour microprocesseur

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DE2853523C2 (de) * 1978-12-12 1981-10-01 Ibm Deutschland Gmbh, 7000 Stuttgart Dezentrale Erzeugung von Taktsteuersignalen
JPS55132278A (en) * 1979-04-02 1980-10-14 Canon Inc Liquid-drip jet recording device
JPS55132277A (en) * 1979-04-02 1980-10-14 Canon Inc Liquid-drip jet recording device
US4344132A (en) * 1979-12-14 1982-08-10 International Business Machines Corporation Serial storage interface apparatus for coupling a serial storage mechanism to a data processor input/output bus
JPS5818411A (ja) * 1981-07-27 1983-02-03 Nippon Ester Co Ltd ポリエステル太細糸
DE3133682A1 (de) * 1981-08-26 1983-03-17 Otto 7750 Konstanz Müller Zentraleinheit eines digitalen rechensystems mit asynchroner taktschaltung
US4872107A (en) * 1983-04-22 1989-10-03 International Business Machines Corporation Floppy disk controller with means to change clock rate automatically
US4819164A (en) * 1983-12-12 1989-04-04 Texas Instruments Incorporated Variable frequency microprocessor clock generator
DE3501569C2 (de) * 1984-01-20 1996-07-18 Canon Kk Datenverarbeitungseinrichtung
US4683551A (en) * 1984-03-28 1987-07-28 Minnesota Mining And Manufacturing Company Ram clock switching circuitry for a laser beam printer
JPS61147386A (ja) * 1984-12-21 1986-07-05 Tokyo Tatsuno Co Ltd Ｉｃカ−ド読取り・書込み装置
JPS61148588A (ja) * 1984-12-22 1986-07-07 Tokyo Tatsuno Co Ltd Ｉｃカ−ド読取り・書込み装置
DE3517662C2 (de) * 1985-05-15 1993-12-02 Siemens Ag Einrichtung zum bedarfsweisen Vermindern eines Verarbeitungstaktes
US4881205A (en) * 1987-04-21 1989-11-14 Casio Computer Co., Ltd. Compact electronic apparatus with a refresh unit for a dynamic type memory
FR2636464B1 (fr) * 1988-09-14 1990-10-26 Sgs Thomson Microelectronics Memoire eprom avec signature interne concernant notamment le mode de programmation
US5680353A (en) * 1988-09-14 1997-10-21 Sgs-Thomson Microelectronics, S.A. EPROM memory with internal signature concerning, in particular, the programming mode
US5197126A (en) * 1988-09-15 1993-03-23 Silicon Graphics, Inc. Clock switching circuit for asynchronous clocks of graphics generation apparatus
US4958309A (en) * 1989-01-30 1990-09-18 Nrc Corporation Apparatus and method for changing frequencies
US5210846B1 (en) * 1989-05-15 1999-06-29 Dallas Semiconductor One-wire bus architecture
WO1990014626A1 (fr) * 1989-05-15 1990-11-29 Dallas Semiconductor Corporation Systemes a jeton de donnee/bus monofil
US5440749A (en) * 1989-08-03 1995-08-08 Nanotronics Corporation High performance, low cost microprocessor architecture
US5218704A (en) 1989-10-30 1993-06-08 Texas Instruments Real-time power conservation for portable computers
US6158012A (en) * 1989-10-30 2000-12-05 Texas Instruments Incorporated Real-time power conservation and thermal management for computers
US5247636A (en) * 1990-05-31 1993-09-21 International Business Machines Corporation Digital processor clock circuit
US5134703A (en) * 1990-06-11 1992-07-28 Nemonix, Inc. External clock unit for a computer
US5155841A (en) * 1990-09-24 1992-10-13 Nemonix, Inc. External clock unit for a computer
JPH04137081A (ja) * 1990-09-28 1992-05-12 Fuji Photo Film Co Ltd Ｅｅｐｒｏｍを有するｉｃメモリカード
DE69229081T2 (de) * 1991-03-01 2000-01-05 Advanced Micro Devices Inc Mikroprozessor mit externem Speicher
US6383747B1 (en) 1991-11-01 2002-05-07 The Immunogenetics Research Foundation Incorporated Method for determining ancestral haplotypes using haplospecific geometric elements within the major histocompatibility complex multigene cluster
US5280587A (en) * 1992-03-31 1994-01-18 Vlsi Technology, Inc. Computer system in which a bus controller varies data transfer rate over a bus based on a value of a subset of address bits and on a stored value
US5903746A (en) * 1996-11-04 1999-05-11 Texas Instruments Incorporated Apparatus and method for automatically sequencing clocks in a data processing system when entering or leaving a low power state
US5790609A (en) * 1996-11-04 1998-08-04 Texas Instruments Incorporated Apparatus for cleanly switching between various clock sources in a data processing system
JPH11231967A (ja) 1998-02-17 1999-08-27 Nec Corp クロック出力回路
DE10148134B4 (de) * 2001-09-28 2007-04-19 Infineon Technologies Ag Verfahren zur Busansteuerung

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623017A (en) * 1969-10-22 1971-11-23 Sperry Rand Corp Dual clocking arrangement for a digital computer
US3703707A (en) * 1971-04-28 1972-11-21 Burroughs Corp Dual clock memory access control
US3764992A (en) * 1972-02-14 1973-10-09 Bell Telephone Labor Inc Program-variable clock pulse generator
US3753232A (en) * 1972-04-06 1973-08-14 Honeywell Inf Systems Memory control system adaptive to different access and cycle times
US3809884A (en) * 1972-11-15 1974-05-07 Honeywell Inf Systems Apparatus and method for a variable memory cycle in a data processing unit
JPS5416836B2 (fr) * 1973-12-03 1979-06-25
US3950735A (en) * 1974-01-04 1976-04-13 Honeywell Information Systems, Inc. Method and apparatus for dynamically controlling read/write operations in a peripheral subsystem
US3984812A (en) * 1974-04-15 1976-10-05 Burroughs Corporation Computer memory read delay
US3980993A (en) * 1974-10-17 1976-09-14 Burroughs Corporation High-speed/low-speed interface for data processing systems
US4050096A (en) * 1974-10-30 1977-09-20 Motorola, Inc. Pulse expanding system for microprocessor systems with slow memory
JPS5247334A (en) * 1975-10-13 1977-04-15 Fujitsu Ltd Memory control system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0212636A2 (fr) * 1985-08-21 1987-03-04 Nec Corporation Circuit de commande de l'état d'un bus
EP0212636A3 (en) * 1985-08-21 1989-07-19 Nec Corporation Bus state control circuit
EP0386935A2 (fr) * 1989-03-08 1990-09-12 Canon Kabushiki Kaisha Appareil capable de varier le nombre d'états d'attente pour accès
EP0386935A3 (fr) * 1989-03-08 1991-06-19 Canon Kabushiki Kaisha Appareil capable de varier le nombre d'états d'attente pour accès
EP0497441A2 (fr) * 1991-01-28 1992-08-05 Advanced Micro Devices, Inc. Système amélioré de chronogramme synchrone pour microprocesseur
EP0497441A3 (en) * 1991-01-28 1993-04-21 Advanced Micro Devices, Inc. Improved microprocessor synchronous timing system

Also Published As

Publication number Publication date
ZA782047B (en) 1979-03-28
FR2388342B1 (fr) 1985-11-22
PL116378B1 (en) 1981-06-30
DE2815283A1 (de) 1978-11-02
PL206189A1 (pl) 1978-12-18
JPS5653781B2 (fr) 1981-12-21
DE2815283C3 (de) 1986-10-23
AU3487178A (en) 1979-10-11
DE2815283B2 (de) 1981-10-01
US4217637A (en) 1980-08-12
NL176715C (nl) 1985-05-17
AU513884B2 (en) 1981-01-08
NL7804033A (nl) 1978-10-24
NL176715B (nl) 1984-12-17
JPS5439538A (en) 1979-03-27
GB1561961A (en) 1980-03-05

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Legal Events

Date Code Title Description
ST Notification of lapse