FR2368784A1 - ROM using MOSFETs - has double injection of electric charges and floating grid - Google Patents

ROM using MOSFETs - has double injection of electric charges and floating grid

Info

Publication number
FR2368784A1
FR2368784A1 FR7631541A FR7631541A FR2368784A1 FR 2368784 A1 FR2368784 A1 FR 2368784A1 FR 7631541 A FR7631541 A FR 7631541A FR 7631541 A FR7631541 A FR 7631541A FR 2368784 A1 FR2368784 A1 FR 2368784A1
Authority
FR
France
Prior art keywords
floating grid
junction
electric charges
memory
injection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7631541A
Other languages
French (fr)
Other versions
FR2368784B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments France SAS
Original Assignee
Texas Instruments France SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments France SAS filed Critical Texas Instruments France SAS
Priority to FR7631541A priority Critical patent/FR2368784A1/en
Priority to JP12808177A priority patent/JPS5466088A/en
Publication of FR2368784A1 publication Critical patent/FR2368784A1/en
Priority to FR7826803A priority patent/FR2437046A2/en
Application granted granted Critical
Publication of FR2368784B1 publication Critical patent/FR2368784B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8616—Charge trapping diodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The permanent or read-only memory has metal oxide field effect semiconductor devices. It stores data by injection of electric charges and it has a floating grid. The memory has a single junction (4) to inject either electrons or holes into a floating grid (8). The charge injection is obtained by inverse polarisation of the junction (4) to a level at least equal to the avalanche threshold. It also has a capacitor to control the operation of the junction (4) in the electron injection or the hole injection mode. The memory also comprises an address transistor between the address terminal and the junction 4), and another transistor to detect the condition of the floating grid.
FR7631541A 1976-10-20 1976-10-20 ROM using MOSFETs - has double injection of electric charges and floating grid Granted FR2368784A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR7631541A FR2368784A1 (en) 1976-10-20 1976-10-20 ROM using MOSFETs - has double injection of electric charges and floating grid
JP12808177A JPS5466088A (en) 1976-10-20 1977-10-25 Semiconductor memory cell
FR7826803A FR2437046A2 (en) 1976-10-20 1978-09-19 Single variable memory cell with floating grid - allows charge injection of electrons of holes by inverse polarisation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7631541A FR2368784A1 (en) 1976-10-20 1976-10-20 ROM using MOSFETs - has double injection of electric charges and floating grid

Publications (2)

Publication Number Publication Date
FR2368784A1 true FR2368784A1 (en) 1978-05-19
FR2368784B1 FR2368784B1 (en) 1980-09-26

Family

ID=9178985

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7631541A Granted FR2368784A1 (en) 1976-10-20 1976-10-20 ROM using MOSFETs - has double injection of electric charges and floating grid

Country Status (2)

Country Link
JP (1) JPS5466088A (en)
FR (1) FR2368784A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0077520A2 (en) * 1981-10-19 1983-04-27 Deutsche ITT Industries GmbH Floating gate memory cell wherein writing and erasing is performed by injection of hot charge carriers

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3868187A (en) * 1972-08-31 1975-02-25 Tokyo Shibaura Electric Co Avalanche injection type mos memory

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51120679A (en) * 1975-04-16 1976-10-22 Agency Of Ind Science & Technol Semiconductive non-volatile memory element
US4037242A (en) * 1975-12-29 1977-07-19 Texas Instruments Incorporated Dual injector, floating gate MOS electrically alterable, non-volatile semiconductor memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3868187A (en) * 1972-08-31 1975-02-25 Tokyo Shibaura Electric Co Avalanche injection type mos memory

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
EXBK/72 *
EXBK/73 *
EXBK/76 *
NV433/76 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0077520A2 (en) * 1981-10-19 1983-04-27 Deutsche ITT Industries GmbH Floating gate memory cell wherein writing and erasing is performed by injection of hot charge carriers
EP0077520A3 (en) * 1981-10-19 1984-11-28 Deutsche ITT Industries GmbH Floating gate memory cell wherein writing and erasing is performed by injection of hot charge carriers

Also Published As

Publication number Publication date
FR2368784B1 (en) 1980-09-26
JPS5466088A (en) 1979-05-28

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