JPS6413772A - Method of reading semiconductor non-volatile memory - Google Patents

Method of reading semiconductor non-volatile memory

Info

Publication number
JPS6413772A
JPS6413772A JP62170421A JP17042187A JPS6413772A JP S6413772 A JPS6413772 A JP S6413772A JP 62170421 A JP62170421 A JP 62170421A JP 17042187 A JP17042187 A JP 17042187A JP S6413772 A JPS6413772 A JP S6413772A
Authority
JP
Japan
Prior art keywords
reading
volatile memory
currents
vth
trap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62170421A
Other languages
Japanese (ja)
Inventor
Kazutoshi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP62170421A priority Critical patent/JPS6413772A/en
Publication of JPS6413772A publication Critical patent/JPS6413772A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To increase the number of rewriting by forming a transistor detecting the potential of a floating gate electrode and conducting the injection-erasing of charges and reading separately. CONSTITUTION:A reading transistor consisting of a reading gate insulating film 25 and a reading electrode 5 is shaped anew to a floating gate electrode. Iproportional (VG-VTN)<2> holds in the relationship of currents I in a MIS transistor, gate applied voltage VG and threshold voltage VTH. Since VG=0 holds and VTH is brought to the state of depletion on reading, reading currents IR are shown by IRproportional (VTH)<2>. Consequently, when VTH changes by a trap, reading currents alter by the effect of a square. When a non-volatile memory is rewritten, a trap is generated at the nose of a floating gate, and electrons are captured by the trap. Since an injection section and a reading section are separate in the non-volatile memory, reading currents do not vary so far as erasing characteristics do not change. A threshold after injection is reduced after erasing and reading exceed approximately ten thousands in the alteration of the threshold. Accordingly, the number of the rewriting of the non-volatile memory can be increased by one or two figures.
JP62170421A 1987-07-08 1987-07-08 Method of reading semiconductor non-volatile memory Pending JPS6413772A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62170421A JPS6413772A (en) 1987-07-08 1987-07-08 Method of reading semiconductor non-volatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62170421A JPS6413772A (en) 1987-07-08 1987-07-08 Method of reading semiconductor non-volatile memory

Publications (1)

Publication Number Publication Date
JPS6413772A true JPS6413772A (en) 1989-01-18

Family

ID=15904611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62170421A Pending JPS6413772A (en) 1987-07-08 1987-07-08 Method of reading semiconductor non-volatile memory

Country Status (1)

Country Link
JP (1) JPS6413772A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0472241A2 (en) * 1990-08-21 1992-02-26 Philips Patentverwaltung GmbH Electrically programmable and erasable semiconductor memory and its operation method
JP2008130908A (en) * 2006-11-22 2008-06-05 Shindengen Electric Mfg Co Ltd Circuit device equipped with capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0472241A2 (en) * 1990-08-21 1992-02-26 Philips Patentverwaltung GmbH Electrically programmable and erasable semiconductor memory and its operation method
JP2008130908A (en) * 2006-11-22 2008-06-05 Shindengen Electric Mfg Co Ltd Circuit device equipped with capacitor

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