FR2112250A1 - Molydenum gate fet - using doped oxides for diffusion and passivation - Google Patents
Molydenum gate fet - using doped oxides for diffusion and passivationInfo
- Publication number
- FR2112250A1 FR2112250A1 FR7135202A FR7135202A FR2112250A1 FR 2112250 A1 FR2112250 A1 FR 2112250A1 FR 7135202 A FR7135202 A FR 7135202A FR 7135202 A FR7135202 A FR 7135202A FR 2112250 A1 FR2112250 A1 FR 2112250A1
- Authority
- FR
- France
- Prior art keywords
- diffusion
- passivation
- molydenum
- gate
- doped oxides
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 title abstract 4
- 238000002161 passivation Methods 0.000 title abstract 3
- 230000000295 complement effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Formation Of Insulating Films (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US7722270A | 1970-10-01 | 1970-10-01 | |
| US9413870A | 1970-12-01 | 1970-12-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2112250A1 true FR2112250A1 (en) | 1972-06-16 |
| FR2112250B1 FR2112250B1 (enExample) | 1977-08-05 |
Family
ID=26759038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7135202A Granted FR2112250A1 (en) | 1970-10-01 | 1971-09-30 | Molydenum gate fet - using doped oxides for diffusion and passivation |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS5514546B1 (enExample) |
| CH (1) | CH531255A (enExample) |
| FR (1) | FR2112250A1 (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6039939U (ja) * | 1983-08-26 | 1985-03-20 | 株式会社学習研究社 | 上皿てこ式の台はかり |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3566518A (en) * | 1967-10-13 | 1971-03-02 | Gen Electric | Method for fabricating field-effect transistor devices and integrated circuit modules containing the same by selective diffusion of activator impurities through preselected portions of passivating-insulating films |
-
1971
- 1971-09-30 CH CH1423371A patent/CH531255A/de not_active IP Right Cessation
- 1971-09-30 FR FR7135202A patent/FR2112250A1/fr active Granted
- 1971-10-01 JP JP7642671A patent/JPS5514546B1/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CH531255A (de) | 1972-11-30 |
| JPS5514546B1 (enExample) | 1980-04-17 |
| FR2112250B1 (enExample) | 1977-08-05 |
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