FI833637A - Centralenhet foer databehandlingssystem - Google Patents

Centralenhet foer databehandlingssystem Download PDF

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Publication number
FI833637A
FI833637A FI833637A FI833637A FI833637A FI 833637 A FI833637 A FI 833637A FI 833637 A FI833637 A FI 833637A FI 833637 A FI833637 A FI 833637A FI 833637 A FI833637 A FI 833637A
Authority
FI
Finland
Prior art keywords
databehandlingssystem
centralenhet
foer
foer databehandlingssystem
centralenhet foer
Prior art date
Application number
FI833637A
Other languages
English (en)
Other versions
FI80532C (fi
FI80532B (fi
FI833637A0 (fi
Inventor
Leonard G Trubisky
William A Shelly
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Publication of FI833637A0 publication Critical patent/FI833637A0/fi
Publication of FI833637A publication Critical patent/FI833637A/fi
Application granted granted Critical
Publication of FI80532B publication Critical patent/FI80532B/fi
Publication of FI80532C publication Critical patent/FI80532C/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
FI833637A 1982-10-13 1983-10-07 Centralenhet foer databehandlingssystem. FI80532C (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US43412282 1982-10-13
US06/434,122 US4521851A (en) 1982-10-13 1982-10-13 Central processor

Publications (4)

Publication Number Publication Date
FI833637A0 FI833637A0 (fi) 1983-10-07
FI833637A true FI833637A (fi) 1984-04-14
FI80532B FI80532B (fi) 1990-02-28
FI80532C FI80532C (fi) 1990-06-11

Family

ID=23722909

Family Applications (1)

Application Number Title Priority Date Filing Date
FI833637A FI80532C (fi) 1982-10-13 1983-10-07 Centralenhet foer databehandlingssystem.

Country Status (9)

Country Link
US (1) US4521851A (fi)
EP (1) EP0106667B1 (fi)
JP (1) JPS5991546A (fi)
KR (1) KR880002660B1 (fi)
AU (1) AU555456B2 (fi)
CA (1) CA1200318A (fi)
DE (1) DE3377678D1 (fi)
ES (1) ES8406756A1 (fi)
FI (1) FI80532C (fi)

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JPH06100968B2 (ja) * 1986-03-25 1994-12-12 日本電気株式会社 情報処理装置
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JP2810043B2 (ja) * 1987-11-13 1998-10-15 株式会社日立製作所 データ処理装置
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JP2858140B2 (ja) * 1988-10-19 1999-02-17 アポロ・コンピューター・インコーポレーテッド パイプラインプロセッサ装置および方法
US5123097A (en) * 1989-01-05 1992-06-16 Bull Hn Information Systems Inc. Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy
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US5109495A (en) * 1989-02-03 1992-04-28 Digital Equipment Corp. Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor
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US5226126A (en) * 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
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US5230068A (en) * 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
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JP2535252B2 (ja) * 1990-10-17 1996-09-18 三菱電機株式会社 並列処理装置
JP2682232B2 (ja) * 1990-11-21 1997-11-26 松下電器産業株式会社 浮動小数点演算処理装置
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Also Published As

Publication number Publication date
AU555456B2 (en) 1986-09-25
DE3377678D1 (en) 1988-09-15
KR840006528A (ko) 1984-11-30
ES526393A0 (es) 1984-08-01
EP0106667A2 (en) 1984-04-25
EP0106667A3 (en) 1986-04-16
JPS5991546A (ja) 1984-05-26
FI80532C (fi) 1990-06-11
AU1879283A (en) 1984-04-19
FI80532B (fi) 1990-02-28
CA1200318A (en) 1986-02-04
US4521851A (en) 1985-06-04
EP0106667B1 (en) 1988-08-10
ES8406756A1 (es) 1984-08-01
KR880002660B1 (ko) 1988-12-17
FI833637A0 (fi) 1983-10-07

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Owner name: HONEYWELL INFORMATION SYSTEMS INC.