JPS5730042A - Control system for instruction executing sequence - Google Patents

Control system for instruction executing sequence

Info

Publication number
JPS5730042A
JPS5730042A JP10467780A JP10467780A JPS5730042A JP S5730042 A JPS5730042 A JP S5730042A JP 10467780 A JP10467780 A JP 10467780A JP 10467780 A JP10467780 A JP 10467780A JP S5730042 A JPS5730042 A JP S5730042A
Authority
JP
Japan
Prior art keywords
instruction
sequence identifier
cell
control system
execution sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10467780A
Other languages
Japanese (ja)
Inventor
Shigeru Takagi
Masaru Takesue
Kazuo Haruta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10467780A priority Critical patent/JPS5730042A/en
Publication of JPS5730042A publication Critical patent/JPS5730042A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To process a pluraity of instructions in a processor at the same time, by scattering an instruction sequence controlling means into a plurality of operators and making the execution of one instruction asynchronizingly. CONSTITUTION:An instruction fetch controlling means 25 and operating control means 4-6 possible for independent operation of operators 1-3, are provided. The means 25 generates instruction cells including the operator to be used first, types of the operation, an execution sequence identifier TYP and an operand OP, the operating control means designated with the instruction cell is made for the designated operation with the said instruction cell to the operand, the operator to be used next, types of operation and the execution sequence identifier are determined based on the execution sequence identifier indicated with this instruction cell and the instruction cells including them are generated.
JP10467780A 1980-07-30 1980-07-30 Control system for instruction executing sequence Pending JPS5730042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10467780A JPS5730042A (en) 1980-07-30 1980-07-30 Control system for instruction executing sequence

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10467780A JPS5730042A (en) 1980-07-30 1980-07-30 Control system for instruction executing sequence

Publications (1)

Publication Number Publication Date
JPS5730042A true JPS5730042A (en) 1982-02-18

Family

ID=14387094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10467780A Pending JPS5730042A (en) 1980-07-30 1980-07-30 Control system for instruction executing sequence

Country Status (1)

Country Link
JP (1) JPS5730042A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5991547A (en) * 1982-10-13 1984-05-26 ハネウエル・インフオメ−シヨン・システムズ・インコ−ポレ−テツド Collector
JPS5991546A (en) * 1982-10-13 1984-05-26 ハネウエル・インフオメ−シヨンシステムズ・インコ−ポレ−テツド Central processing unit
JPS59161730A (en) * 1983-03-07 1984-09-12 Hitachi Ltd Pipeline computing element
JPH0695872A (en) * 1992-05-06 1994-04-08 Internatl Business Mach Corp <Ibm> Performance controlling device and performing method for data operation in pipeline of variable input/output stage instruction

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5991547A (en) * 1982-10-13 1984-05-26 ハネウエル・インフオメ−シヨン・システムズ・インコ−ポレ−テツド Collector
JPS5991546A (en) * 1982-10-13 1984-05-26 ハネウエル・インフオメ−シヨンシステムズ・インコ−ポレ−テツド Central processing unit
JPS6353571B2 (en) * 1982-10-13 1988-10-24 Haneiueru Infuoomeishon Shisutemusu Inc
JPS59161730A (en) * 1983-03-07 1984-09-12 Hitachi Ltd Pipeline computing element
JPH0534696B2 (en) * 1983-03-07 1993-05-24 Hitachi Ltd
JPH0695872A (en) * 1992-05-06 1994-04-08 Internatl Business Mach Corp <Ibm> Performance controlling device and performing method for data operation in pipeline of variable input/output stage instruction

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