DE3775299D1 - Zentrale recheneinheit. - Google Patents

Zentrale recheneinheit.

Info

Publication number
DE3775299D1
DE3775299D1 DE8787900895T DE3775299T DE3775299D1 DE 3775299 D1 DE3775299 D1 DE 3775299D1 DE 8787900895 T DE8787900895 T DE 8787900895T DE 3775299 T DE3775299 T DE 3775299T DE 3775299 D1 DE3775299 D1 DE 3775299D1
Authority
DE
Germany
Prior art keywords
central computer
computer
central
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787900895T
Other languages
English (en)
Inventor
Joji Murakami
Kenji Yamada
Hideki Isobe
Toshiyuki Igarashi
Yoshihiro Kubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3775299D1 publication Critical patent/DE3775299D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
DE8787900895T 1986-01-27 1987-01-27 Zentrale recheneinheit. Expired - Fee Related DE3775299D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1520586 1986-01-27
PCT/JP1987/000052 WO1987004541A1 (en) 1986-01-27 1987-01-27 Central processing unit

Publications (1)

Publication Number Publication Date
DE3775299D1 true DE3775299D1 (de) 1992-01-30

Family

ID=11882366

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787900895T Expired - Fee Related DE3775299D1 (de) 1986-01-27 1987-01-27 Zentrale recheneinheit.

Country Status (5)

Country Link
US (1) US5001629A (de)
EP (1) EP0256134B1 (de)
KR (1) KR910001708B1 (de)
DE (1) DE3775299D1 (de)
WO (1) WO1987004541A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367650A (en) * 1992-07-31 1994-11-22 Intel Corporation Method and apparauts for parallel exchange operation in a pipelined processor
US6009508A (en) * 1994-06-21 1999-12-28 Sgs-Thomson Microelectronics Limited System and method for addressing plurality of data values with a single address in a multi-value store on FIFO basis
US6112018A (en) * 1997-12-18 2000-08-29 Advanced Micro Devices, Inc. Apparatus for exchanging two stack registers
DE19837101C2 (de) * 1998-08-17 2000-11-23 Philips Corp Intellectual Pty Programmierbare 1-Bit Datenverarbeitungsanordnung
US7080183B1 (en) * 2000-08-16 2006-07-18 Koninklijke Philips Electronics N.V. Reprogrammable apparatus supporting the processing of a digital signal stream and method
US7680990B2 (en) * 2003-05-30 2010-03-16 Hewlett-Packard Development Company, L.P. Superword memory-access instructions for data processor

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS512302A (en) * 1974-06-24 1976-01-09 Fujitsu Ltd Johotensohoshiki
US4323964A (en) * 1976-11-01 1982-04-06 Data General Corporation CPU Employing micro programmable control for use in a data processing system
JPS5833572B2 (ja) * 1977-10-21 1983-07-20 株式会社東芝 情報処理方式
US4266270A (en) * 1978-09-05 1981-05-05 Motorola, Inc. Microprocessor having plural internal data buses
JPS5730167A (en) * 1980-07-30 1982-02-18 Fujitsu Ltd Stack memory device
US4472773A (en) * 1981-09-16 1984-09-18 Honeywell Information Systems Inc. Instruction decoding logic system
US4541045A (en) * 1981-09-21 1985-09-10 Racal-Milgo, Inc. Microprocessor architecture employing efficient operand and instruction addressing
JPS5880740A (ja) * 1981-11-09 1983-05-14 Nec Corp マイクロプログラム制御装置
US4521851A (en) * 1982-10-13 1985-06-04 Honeywell Information Systems Inc. Central processor
JPS62165242A (ja) * 1986-01-17 1987-07-21 Toshiba Corp プロセツサ

Also Published As

Publication number Publication date
WO1987004541A1 (en) 1987-07-30
EP0256134B1 (de) 1991-12-18
EP0256134A4 (de) 1988-05-02
EP0256134A1 (de) 1988-02-24
US5001629A (en) 1991-03-19
KR910001708B1 (ko) 1991-03-19
KR880700968A (ko) 1988-04-13

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee