FI122301B - Piiri, menetelmä ja järjestely yksinkertaisen ja luotettavan hajautetun väyläarbitroinnin toteuttamiseksi - Google Patents
Piiri, menetelmä ja järjestely yksinkertaisen ja luotettavan hajautetun väyläarbitroinnin toteuttamiseksi Download PDFInfo
- Publication number
- FI122301B FI122301B FI20060767A FI20060767A FI122301B FI 122301 B FI122301 B FI 122301B FI 20060767 A FI20060767 A FI 20060767A FI 20060767 A FI20060767 A FI 20060767A FI 122301 B FI122301 B FI 122301B
- Authority
- FI
- Finland
- Prior art keywords
- bus line
- bus
- arrangement
- circuit
- arbitration
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 19
- 230000008859 change Effects 0.000 claims description 13
- 230000000694 effects Effects 0.000 claims description 9
- 230000004044 response Effects 0.000 claims description 7
- 230000004913 activation Effects 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims 1
- 230000006870 function Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 5
- 238000012913 prioritisation Methods 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 4
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 description 4
- 238000004891 communication Methods 0.000 description 4
- 230000001934 delay Effects 0.000 description 4
- 230000003993 interaction Effects 0.000 description 4
- 230000001419 dependent effect Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000009849 deactivation Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 101100021265 Caenorhabditis elegans lin-5 gene Proteins 0.000 description 1
- 101100172132 Mus musculus Eif3a gene Proteins 0.000 description 1
- 238000013475 authorization Methods 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
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- 230000011664 signaling Effects 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
- 230000008685 targeting Effects 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
- H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
- H04L12/4135—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD] using bit-wise arbitration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40032—Details regarding a bus interface enhancer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20060767A FI122301B (fi) | 2006-08-25 | 2006-08-25 | Piiri, menetelmä ja järjestely yksinkertaisen ja luotettavan hajautetun väyläarbitroinnin toteuttamiseksi |
JP2009526141A JP4824111B2 (ja) | 2006-08-25 | 2007-08-24 | バス上で単純かつ高い信頼度の分散アービトレーションを行うための回路、方法及び装置 |
PCT/FI2007/000210 WO2008023091A1 (fr) | 2006-08-25 | 2007-08-24 | Circuit, procédé et agencement pour implémenter un arbitrage distribué simple et fiable sur un bus |
US12/310,458 US8190802B2 (en) | 2006-08-25 | 2007-08-24 | Circuit, method and arrangement for implementing simple and reliable distributed arbitration on a bus |
EP07823073.7A EP2054809B1 (fr) | 2006-08-25 | 2007-08-24 | Circuit, procédé et agencement pour implémenter un arbitrage distribué simple et fiable sur un bus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20060767 | 2006-08-25 | ||
FI20060767A FI122301B (fi) | 2006-08-25 | 2006-08-25 | Piiri, menetelmä ja järjestely yksinkertaisen ja luotettavan hajautetun väyläarbitroinnin toteuttamiseksi |
Publications (3)
Publication Number | Publication Date |
---|---|
FI20060767A0 FI20060767A0 (fi) | 2006-08-25 |
FI20060767A FI20060767A (fi) | 2008-02-26 |
FI122301B true FI122301B (fi) | 2011-11-30 |
Family
ID=36950668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI20060767A FI122301B (fi) | 2006-08-25 | 2006-08-25 | Piiri, menetelmä ja järjestely yksinkertaisen ja luotettavan hajautetun väyläarbitroinnin toteuttamiseksi |
Country Status (5)
Country | Link |
---|---|
US (1) | US8190802B2 (fr) |
EP (1) | EP2054809B1 (fr) |
JP (1) | JP4824111B2 (fr) |
FI (1) | FI122301B (fr) |
WO (1) | WO2008023091A1 (fr) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7865629B1 (en) | 2009-11-24 | 2011-01-04 | Microsoft Corporation | Configurable connector for system-level communication |
US8719112B2 (en) | 2009-11-24 | 2014-05-06 | Microsoft Corporation | Invocation of accessory-specific user experience |
DE102011007437A1 (de) * | 2010-11-15 | 2012-05-16 | Continental Teves Ag & Co. Ohg | Verfahren und Schaltungsanrodnung zur Datenübertragung zwischen Prozessorbausteinen |
US8984194B2 (en) * | 2011-01-21 | 2015-03-17 | Numia Medical Technology Llc | Multi-master bus arbitration and resource control |
US8856415B2 (en) | 2012-02-01 | 2014-10-07 | National Instruments Corporation | Bus arbitration for a real-time computer system |
US8793697B2 (en) * | 2012-02-23 | 2014-07-29 | Qualcomm Incorporated | Method and system for scheduling requests in a portable computing device |
US9430421B2 (en) * | 2014-03-12 | 2016-08-30 | Arm Limited | Interrupt signal arbitration |
EP3729739B1 (fr) * | 2017-12-24 | 2023-08-23 | Technion Research & Development Foundation Limited | Authentification de message basée sur un emplacement physique sur un bus |
CN111400239A (zh) * | 2020-04-15 | 2020-07-10 | 联合华芯电子有限公司 | 片内分布式互联总线系统及多核处理器 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3170828D1 (en) * | 1980-07-08 | 1985-07-11 | Thomson Csf Mat Tel | Method and apparatus for arbitrating between a plurality of sub-systems |
US5111424A (en) | 1987-05-01 | 1992-05-05 | Digital Equipment Corporation | Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfer |
US5160922A (en) * | 1990-06-29 | 1992-11-03 | Digital Equipment Corporation | System and method for dynamic avoidance of a simultaneous switching output limitation of a integrated circuit chip |
DE69227996T2 (de) * | 1991-07-26 | 1999-08-26 | Tandem Computers Inc. | Vorrichtung und verfahren zur vermittlung von datenblöcken |
JPH05242048A (ja) * | 1992-03-02 | 1993-09-21 | Meidensha Corp | マルチ・プロセッサ・システムの直列調停方法およびその装置 |
JPH0660018A (ja) * | 1992-08-11 | 1994-03-04 | Fujitsu Ltd | バスアービトレーション方法、アービタ回路及びアービタ |
US5430848A (en) | 1992-08-14 | 1995-07-04 | Loral Fairchild Corporation | Distributed arbitration with programmable priorities |
US5437042A (en) * | 1992-10-02 | 1995-07-25 | Compaq Computer Corporation | Arrangement of DMA, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system |
US5404538A (en) * | 1992-10-28 | 1995-04-04 | International Business Machines Corporation | Method and apparatus for multilevel bus arbitration |
JPH0793316B2 (ja) | 1992-12-28 | 1995-10-09 | 日本電気株式会社 | 半導体装置の製造方法 |
US5579486A (en) * | 1993-01-14 | 1996-11-26 | Apple Computer, Inc. | Communication node with a first bus configuration for arbitration and a second bus configuration for data transfer |
US5455912A (en) * | 1993-06-18 | 1995-10-03 | Vtech Industries, Inc. | High speed/low overhead bus arbitration apparatus and method for arbitrating a system bus |
US5710891A (en) | 1995-03-31 | 1998-01-20 | Sun Microsystems, Inc. | Pipelined distributed bus arbitration system |
US5933648A (en) * | 1996-12-20 | 1999-08-03 | Intel Corporation | Configurable arbitration device for controlling the access of components to an arbiter or the like based on a control input |
US5931924A (en) * | 1997-04-14 | 1999-08-03 | International Business Machines Corporation | Method and system for controlling access to a shared resource that each requestor is concurrently assigned at least two pseudo-random priority weights |
KR100252752B1 (ko) * | 1997-06-26 | 2000-04-15 | 김영환 | 다단계 제어 버스 중재장치 |
US6327696B1 (en) | 1998-05-05 | 2001-12-04 | Lsi Logic Corporation | Method and apparatus for zero skew routing from a fixed H trunk |
US6167478A (en) * | 1998-10-05 | 2000-12-26 | Infineon Technologies North America Corp. | Pipelined arbitration system and method |
US6587905B1 (en) * | 2000-06-29 | 2003-07-01 | International Business Machines Corporation | Dynamic data bus allocation |
US6993612B2 (en) * | 2000-12-07 | 2006-01-31 | Micron Technology, Inc. | Arbitration method for a source strobed bus |
US6948019B2 (en) * | 2002-04-30 | 2005-09-20 | Lsi Logic Corporation | Apparatus for arbitrating non-queued split master devices on a data bus |
JP4182801B2 (ja) * | 2003-04-24 | 2008-11-19 | 日本電気株式会社 | マルチプロセサシステム |
US7493511B1 (en) * | 2004-08-27 | 2009-02-17 | Xilinx, Inc. | Network media access controller embedded in a programmable logic device—transmit-side client interface |
CN101427535A (zh) * | 2006-04-24 | 2009-05-06 | 皇家飞利浦电子股份有限公司 | 具有消息的端到端流控制的电子设备 |
US20110022754A1 (en) * | 2007-12-06 | 2011-01-27 | Technion Research & Development Foundation Ltd | Bus enhanced network on chip |
-
2006
- 2006-08-25 FI FI20060767A patent/FI122301B/fi not_active IP Right Cessation
-
2007
- 2007-08-24 WO PCT/FI2007/000210 patent/WO2008023091A1/fr active Application Filing
- 2007-08-24 JP JP2009526141A patent/JP4824111B2/ja not_active Expired - Fee Related
- 2007-08-24 EP EP07823073.7A patent/EP2054809B1/fr not_active Not-in-force
- 2007-08-24 US US12/310,458 patent/US8190802B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP2054809B1 (fr) | 2013-05-22 |
US8190802B2 (en) | 2012-05-29 |
JP4824111B2 (ja) | 2011-11-30 |
EP2054809A4 (fr) | 2012-07-18 |
WO2008023091A1 (fr) | 2008-02-28 |
JP2010501954A (ja) | 2010-01-21 |
FI20060767A0 (fi) | 2006-08-25 |
FI20060767A (fi) | 2008-02-26 |
EP2054809A1 (fr) | 2009-05-06 |
US20090319709A1 (en) | 2009-12-24 |
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