FI113572B - Virkistysmenetelmä DRAM:eja varten - Google Patents

Virkistysmenetelmä DRAM:eja varten

Info

Publication number
FI113572B
FI113572B FI972050A FI972050A FI113572B FI 113572 B FI113572 B FI 113572B FI 972050 A FI972050 A FI 972050A FI 972050 A FI972050 A FI 972050A FI 113572 B FI113572 B FI 113572B
Authority
FI
Finland
Prior art keywords
dram memories
refresh procedure
refresh
procedure
dram
Prior art date
Application number
FI972050A
Other languages
English (en)
Finnish (fi)
Swedish (sv)
Other versions
FI972050A0 (fi
FI972050L (fi
Inventor
L Randall Mote Jr
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FI972050A0 publication Critical patent/FI972050A0/fi
Publication of FI972050L publication Critical patent/FI972050L/fi
Application granted granted Critical
Publication of FI113572B publication Critical patent/FI113572B/fi

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
FI972050A 1995-09-14 1997-05-14 Virkistysmenetelmä DRAM:eja varten FI113572B (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/527,950 US5654929A (en) 1995-09-14 1995-09-14 Refresh strategy for DRAMs
PCT/US1996/010854 WO1997010601A1 (en) 1995-09-14 1996-06-27 Refresh strategy for drams

Publications (3)

Publication Number Publication Date
FI972050A0 FI972050A0 (fi) 1997-05-14
FI972050L FI972050L (fi) 1997-05-14
FI113572B true FI113572B (fi) 2004-05-14

Family

ID=24103635

Family Applications (1)

Application Number Title Priority Date Filing Date
FI972050A FI113572B (fi) 1995-09-14 1997-05-14 Virkistysmenetelmä DRAM:eja varten

Country Status (12)

Country Link
US (1) US5654929A (ref)
EP (1) EP0792506B1 (ref)
JP (1) JP4166274B2 (ref)
KR (1) KR100248259B1 (ref)
CN (1) CN1130730C (ref)
AU (1) AU6393496A (ref)
DE (1) DE69621419T2 (ref)
FI (1) FI113572B (ref)
IN (1) IN192635B (ref)
RU (1) RU2163035C2 (ref)
TW (1) TW303469B (ref)
WO (2) WO1997010602A1 (ref)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610493B1 (en) 1993-06-17 2003-08-26 Brigham And Women's Hospital Screening compounds for the ability to alter the production of amyloid-β peptide
US5841686A (en) * 1996-11-22 1998-11-24 Ma Laboratories, Inc. Dual-bank memory module with shared capacitors and R-C elements integrated into the module substrate
KR100243335B1 (ko) * 1996-12-31 2000-02-01 김영환 독립적인 리프레쉬 수단을 가지는 데이지 체인 구조의 반도체 장치
DE19855445C1 (de) * 1998-12-01 2000-02-24 Siemens Ag Vorrichtung zur Verringerung der elektromagnetischen Emission bei integrierten Schaltungen mit Treiberstufen
JP4270707B2 (ja) * 1999-04-09 2009-06-03 株式会社東芝 ダイナミック型半導体記憶装置
US7124285B2 (en) * 2001-03-29 2006-10-17 Intel Corporation Peak power reduction when updating future file
US6532175B1 (en) * 2002-01-16 2003-03-11 Advanced Micro Devices, In. Method and apparatus for soft program verification in a memory device
CN101042933B (zh) * 2007-04-12 2010-05-19 复旦大学 非挥发sram单元、阵列及其操作方法和应用
CN101504865B (zh) * 2009-03-06 2011-06-22 成都市华为赛门铁克科技有限公司 存储系统的数据处理方法及存储设备
JP6314673B2 (ja) * 2014-06-11 2018-04-25 富士電機株式会社 半導体装置
KR20160013624A (ko) * 2014-07-28 2016-02-05 에스케이하이닉스 주식회사 리프레쉬 회로
US10490251B2 (en) 2017-01-30 2019-11-26 Micron Technology, Inc. Apparatuses and methods for distributing row hammer refresh events across a memory device
KR20190075341A (ko) 2017-12-21 2019-07-01 에스케이하이닉스 주식회사 반도체 메모리 장치
US11200944B2 (en) 2017-12-21 2021-12-14 SK Hynix Inc. Semiconductor memory apparatus operating in a refresh mode and method for performing the same
WO2019222960A1 (en) 2018-05-24 2019-11-28 Micron Technology, Inc. Apparatuses and methods for pure-time, self adopt sampling for row hammer refresh sampling
US10573370B2 (en) 2018-07-02 2020-02-25 Micron Technology, Inc. Apparatus and methods for triggering row hammer address sampling
US10685696B2 (en) 2018-10-31 2020-06-16 Micron Technology, Inc. Apparatuses and methods for access based refresh timing
CN113168861B (zh) 2018-12-03 2024-05-14 美光科技公司 执行行锤刷新操作的半导体装置
CN117198356A (zh) 2018-12-21 2023-12-08 美光科技公司 用于目标刷新操作的时序交错的设备和方法
US10957377B2 (en) 2018-12-26 2021-03-23 Micron Technology, Inc. Apparatuses and methods for distributed targeted refresh operations
US11615831B2 (en) * 2019-02-26 2023-03-28 Micron Technology, Inc. Apparatuses and methods for memory mat refresh sequencing
US11227649B2 (en) 2019-04-04 2022-01-18 Micron Technology, Inc. Apparatuses and methods for staggered timing of targeted refresh operations
US11069393B2 (en) 2019-06-04 2021-07-20 Micron Technology, Inc. Apparatuses and methods for controlling steal rates
US10978132B2 (en) 2019-06-05 2021-04-13 Micron Technology, Inc. Apparatuses and methods for staggered timing of skipped refresh operations
US11302374B2 (en) 2019-08-23 2022-04-12 Micron Technology, Inc. Apparatuses and methods for dynamic refresh allocation
US11302377B2 (en) 2019-10-16 2022-04-12 Micron Technology, Inc. Apparatuses and methods for dynamic targeted refresh steals
US11309010B2 (en) 2020-08-14 2022-04-19 Micron Technology, Inc. Apparatuses, systems, and methods for memory directed access pause
US11380382B2 (en) 2020-08-19 2022-07-05 Micron Technology, Inc. Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit
US11348631B2 (en) 2020-08-19 2022-05-31 Micron Technology, Inc. Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed
US11557331B2 (en) 2020-09-23 2023-01-17 Micron Technology, Inc. Apparatuses and methods for controlling refresh operations
US11222686B1 (en) 2020-11-12 2022-01-11 Micron Technology, Inc. Apparatuses and methods for controlling refresh timing
US11264079B1 (en) 2020-12-18 2022-03-01 Micron Technology, Inc. Apparatuses and methods for row hammer based cache lockdown
US12125514B2 (en) 2022-04-28 2024-10-22 Micron Technology, Inc. Apparatuses and methods for access based refresh operations
US12112787B2 (en) 2022-04-28 2024-10-08 Micron Technology, Inc. Apparatuses and methods for access based targeted refresh operations

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4887240A (en) * 1987-12-15 1989-12-12 National Semiconductor Corporation Staggered refresh for dram array
US5113372A (en) * 1990-06-06 1992-05-12 Micron Technology, Inc. Actively controlled transient reducing current supply and regulation circuits for random access memory integrated circuits
JPH06338187A (ja) * 1993-05-27 1994-12-06 Melco:Kk Dramを用いたメモリ装置
US5465237A (en) * 1994-12-01 1995-11-07 Advanced Peripherals Labs, Inc. RAS encoded generator for a memory bank

Also Published As

Publication number Publication date
WO1997010602A1 (en) 1997-03-20
KR970707554A (ko) 1997-12-01
EP0792506A1 (en) 1997-09-03
IN192635B (ref) 2004-05-08
DE69621419D1 (de) 2002-07-04
CN1130730C (zh) 2003-12-10
JPH10509269A (ja) 1998-09-08
KR100248259B1 (ko) 2000-03-15
WO1997010601A1 (en) 1997-03-20
DE69621419T2 (de) 2003-01-16
CN1169205A (zh) 1997-12-31
AU6393496A (en) 1997-04-01
FI972050A0 (fi) 1997-05-14
JP4166274B2 (ja) 2008-10-15
EP0792506A4 (en) 1998-08-19
EP0792506B1 (en) 2002-05-29
TW303469B (ref) 1997-04-21
FI972050L (fi) 1997-05-14
US5654929A (en) 1997-08-05
RU2163035C2 (ru) 2001-02-10

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